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4.3.25. TLB lockdown operations

TLB lockdown operations enable saving or restoring lockdown entries in the TLB. Table 4.50 shows the defined TLB lockdown operations.

Table 4.50. TLB lockdown operations
DescriptionDataInstruction
Select Lockdown TLB Entry for ReadMain TLB IndexMCR p15,5,<Rd>,c15,c4,2
Select Lockdown TLB Entry for WriteMain TLB IndexMCR p15,5,<Rd>,c15,c4,4
Read Lockdown TLB VA RegisterDataMRC p15,5,<Rd>,c15,c5,2
Write Lockdown TLB VA RegisterDataMCR p15,5,<Rd>,c15,c5,2
Read Lockdown TLB PA RegisterDataMRC p15,5,<Rd>,c15,c6,2
Write Lockdown TLB PA RegisterDataMCR p15,5,<Rd>,c15,c6,2
Read Lockdown TLB attributes RegisterDataMRC p15,5,<Rd>,c15,c7,2
Write Lockdown TLB attributes RegisterDataMCR p15,5,<Rd>,c15,c7,2

The Select Lockdown TLB entry for a read operation is used to select the entry that the data read by a read Lockdown TLB VA/PA/attributes operations are coming from. The Select Lockdown TLB entry for a write operation is used to select the entry that the data write Lockdown TLB VA/PA/attributes data are written to. The TLB PA register must be the last written or read register when accessing TLB lockdown registers. Figure 4.24 shows the bit assignment of the index register used to access the lockdown TLB entries.

Figure 4.24. Lockdown TLB index bit assignments

Figure 4.24. Lockdown TLB index bit assignments

Figure 4.25 shows the bit arrangement of the TLB VA Register format.

Figure 4.25. TLB VA Register bit assignments

Figure 4.25. TLB VA Register bit assignments

Table 4.51 shows the TLB VA Register bit assignments.

Table 4.51. TLB VA Register bit assignments
BitsNameFunction
[31:12]VPN

Virtual page number.

Bits of the virtual page number that are not translated as part of the page table translation because the size of the tables is unpredictable when read and SBZ when written.

[11]-UNK/SBZP.
[10]NSNS bit.
[9:0]Process

Memory space identifier.


Figure 4.26 shows the bit arrangement of the memory space identifier.

Figure 4.26. Memory space identifier format

Figure 4.26. Memory space identifier format

Figure 4.27 shows the TLB PA Register bit assignment.

Figure 4.27. TLB PA Register bit assignments

Figure 4.27. TLB PA Register bit assignments

Table 4.52 describes the functions of the TLB PA Register bits.

Table 4.52. TLB PA Register bit assignments
BitsNameFunction
[31:12]PPN

Physical Page Number.

Bits of the physical page number that are not translated as part of the page table translation are unpredictable when read and SBZP when written.

[11:8]-UNK/SBZP.
[7:6]SZ

Region Size:

b00

16MB Supersection

b01

4KB page

b10

64KB page

b11

1MB section.

All other values are reserved.

[5:4]-UNK/SBZP.
[3:1]AP

Access permission:

b000

All accesses generate a permission fault

b001

Supervisor access only, User access generates a fault

b010

Supervisor read/write access, User write access generates a fault

b011

Full access, no fault generated

b100

Reserved

b101

Supervisor read-only

b110

Supervisor/User read-only

b111

Supervisor/User read-only.

[0]V

Value bit.

Indicates that this entry is locked and valid.


Figure 4.28 shows the bit assignments of the TLB Attributes Register.

Figure 4.28. Main TLB Attributes Register bit assignments

Figure 4.28. Main TLB Attributes Register bit assignments

Table 4.53 shows the TLB Attributes Register bit assignments. The Cortex-A9 processor does not support subpages.

Table 4.53. TLB Attributes Register bit assignments
BitsNameFunction
[31:12]-UNK/SBZP.
[11]NSNon-secure description.
[10:7]DomainDomain number of the TLB entry.
[6]XNExecute Never attribute.
[5:3]TEX

Region type encoding. See the ARM Architecture Reference Manual.

[2:1]CB
[0]S Shared attribute.

Invalidate TLB Entries on ASID Match

This is a single operation that invalidates all TLB entries that match the provided Address Space Identifier (ASID) value. This function invalidates locked entries. Entries marked as global are not invalidated by this function.

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