This section gives a summary of the CP15 system control registers. For more information on using the CP15 system control registers, see the ARM Architecture Reference Manual.
The system control coprocessor is a set of registers that you can write to and read from. Some of these registers support more than one type of operation.
This section describes the CP15 system control registers grouped
by CRn order, and accessed by the
in the order of CRn, Op1, CRm, Op2:
All system control coprocessor registers are 32 bits wide, except for the Program New Channel operation described in PLE Program New Channel operation. Reserved registers are RAZ/WI.
In addition to listing the CP15 system control registers by CRn ordering, the following subsections describe the CP15 system control registers by functional group:
Table 4.1 describes the column headings that the CP15 register summary tables use throughout this section.
|CRn||Register number within the system control coprocessor|
|Op1||Opcode_1 value for the register|
|CRm||Operational register number within CRn|
|Op2||Opcode_2 value for the register|
|Name||Short form architectural, operation, or code name for the register|
|Reset||Reset value of register|
|Description||Cross-reference to register description|