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4.2.16. c15 registers

Table 4.15 shows the CP15 system control registers you can access when CRn is c15.

Table 4.15. c15 system control register summary
0c00Power Control RegisterRW[a]

- [b]

Power Control Register
c10NEON Busy RegisterRO0x00000000NEON Busy Register
4c00Configuration Base AddressRO[c]

- [d]

Configuration Base Address Register
5c42Select Lockdown TLB Entry for read WO[e]-TLB lockdown operations
4Select Lockdown TLB Entry for writeWO[e]-
c52Main TLB VA registerRW[e]-
c62Main TLB PA registerRW[e]-
c72Main TLB Attribute registerRW[e]-

[a] RW in Secure state. RO in Non-secure state.

[b] Reset value depends on the MAXCLKLATENCY[2:0] value. See Configuration signals.

[c] RW in secure privileged mode and RO in Non-secure state and User secure state.

[d] In Cortex-A9 uniprocessor implementations the configuration base address is set to zero.

In Cortex-A9 MPCore implementations the configuration base address is reset to PERIPHBASE[31:13] so that software can determine

the location of the private memory region.

[e] No access in Non-secure state.

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