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10.4. Debug register summary

You can access the debug registers:

  • through the CP14 interface. The debug registers are mapped to coprocessor instructions.

  • through the APB using the relevant offset when PADDRDBG[12]=0, with the following exceptions:

    • DBGRAR

    • DBGSAR

    • DBGSCR-int

    • DBGTR-int.

External views of DBSCR and DBGTR are accessible through memory-mapped APB access.

Table 10.1 shows the CP14 interface registers. All other registers are described in the ARM Architecture Reference Manual.

Table 10.1. CP14 Debug register summary
Register number Offset CRn Op1CRmOp2Name TypeDescription
00x000c00c00

DBGDIDR[a][b]

ROSee the ARM Architecture Reference Manual
-- c10c00DBGDRAR[a]RO
-- c20c00

DBGDSAR[a]

RO
-- c00c10

DBGDSCRint[a][b]

RO
5- c00c50

DBGDTRRXint[a]

RO
   DBGDTRTXint[a]WOReserved
6 0x018 c0 0c60DBGWFAR RWUse of DBGWFAR is deprecated in the ARMv7 architecture, because watchpoints are synchronous
7 0x01C c00c70DBGVCR RWSee the ARM Architecture Reference Manual
8 -------Reserved
9 0x024 c00c90DBGECR RAZ/WINot implemented
10 0x028 c00c100DBGDSCCR RAZ/WI
11 0x02Cc00c110DBGDSMCR RAZ/WI
12-31 -------Reserved
32 0x080 c00c02DBGDTRRXextRWSee the ARM Architecture Reference Manual
33 0x084 c00c12DBGITR WO
33 0x084c00c12DBGPCSR RO
34 0x088c00c22DBGDSCRextRW
35 0x08Cc00c32DBGDTRTXextRW
36 0x090c00c42DBGDRCR WOSee the ARM Architecture Reference Manual
37-63 -----Reserved -Reserved
64-68

0x100- 0x114

c00c0-c54DBGBVRn RWBreakpoint Value Registers
69-79-------Reserved
80-85

0x140- 0x154

c00c0-c55DBGBCRn RWBreakpoint Control Registers
86-95--    -Reserved
96-99

0x180- 0x18C

c00c0-c36DBGWVRn RWWatchpoint Value Registers
100-111-------Reserved
112-115

0x1C0- 0x1CC

c00c0-c37DBGWCRn RWWatchpoint Control Registers
116-191 -------Reserved
192 0x300c10c04DBGOSLAR RAZ/WINot implemented
193 0x304c10c14DBGOSLSR RAZ/WI
194 0x308c10c24DBGOSSRRRAZ/WI
195 -------Reserved
196 0x310c10c44DBGPRCR ROSee the ARM Architecture Reference Manual
197 0x314c10c54DBGPRSR RO
198-831 -------Reserved
832-895

0xD00- 0xDFC

----Processor ID Registers[c]ROIdentification Registers
896-927 0xE00- 0xE7C------Reserved
928-959

0xE80- 0xEFC

c70c015, 2-3-RAZ/WIReserved
960-10230xF00- 0xFFC----Debug Management Registers-Debug management registers

[a] Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface.

[b] Accessible in User mode if bit [12] of the DBGSCR is clear. Also accessible in privileged modes.

[c] The Extended CP14 interface MRC and MCR instructions that map to these registers are undefined in User mode and unpredictable in privileged modes. You must use the CP15 interface to access these registers.


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