You copied the Doc URL to your clipboard.

2.3.2. Reset

The Cortex-A9 processor has the following reset inputs:

nCPURESET

The nCPURESET signal is the main Cortex-A9 processor reset. It initializes the Cortex-A9 processor logic and the FPU logic including the FPU register file when the MPE or FPU option is present.

nNEONRESET

The nNEONRESET signal is the reset that controls the NEON SIMD independently of the main Cortex-A9 processor reset.

nDBGRESET

The nDBGRESET signal is the reset that initializes the debug logic. See Chapter 10 Debug.

All of these are active-LOW signals.

Reset modes

The reset signals present in the Cortex-A9 design enable you to reset different parts of the processor independently. Table 2.1 shows the reset signals, and the combinations and possible applications that you can use them in.

Table 2.1. Reset modes
ModenCPURESETnNEONRESETnDBGRESET

Power-on reset, cold reset

000

Processor reset, soft or warm reset

001
SIMD MPE power-on reset101
Debug logic reset110

No reset, normal run mode

111

Power-on reset

You must apply power-on or cold reset to the Cortex-A9 uniprocessor when power is first applied to the system. In the case of power-on reset, the leading edge, that is the falling edge, of the reset signals do not have to be synchronous to CLK, but the rising edge must be.

You must assert the reset signals for at least nine CLK cycles to ensure correct reset behavior.

ARM recommends the following reset sequence:

  1. Apply nCPURESET and nDBGRESET, plus nNEONRESET if the SIMD MPE is present.

  2. Wait for at least nine CLK cycles, plus at least one cycle in each other clock domain, or more if the documentation for other components requires it. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by applying 15 cycles on every clock domain.

  3. Stop the CLK clock input to the Cortex-A9 uniprocessor. If there is a data engine present, use NEONCLKOFF. See Configuration signals.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release all resets.

  6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock and reset tree latencies.

  7. Restart the clock.

Software reset

A processor or warm reset initializes the majority of the Cortex-A9 processor, apart from its debug logic. Breakpoints and watchpoints are retained during a processor reset. Processor reset is typically used for resetting a system that has been operating for some time. Use the same reset sequence described in Power-on reset with the only difference that nDBGRESET must remain HIGH during the sequence, to ensure that all values in the debug registers are maintained.

Processor reset

A processor or warm reset initializes the majority of the Cortex-A9 processor, apart from its debug logic. Breakpoints and watchpoints are retained during a processor reset. Processor reset is typically used for resetting a system that has been operating for some time. Use nCPURESET and nNEONRESET for a warm reset.

MPE SIMD logic reset

This reset initializes all the SIMD logic of the MPE. It is expected to be applied when the SIMD part of the MPE exits from powerdown state. This reset only applies to configurations where the SIMD MPE logic is implemented in its own dedicated power domain, separated from the rest of the processor logic.

ARM recommends the following reset sequence for an MPE SIMD reset:

  1. Apply nNEONRESET.

  2. Wait for at least nine CLK cycles. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by for example applying 15 cycles on every clock domain.

  3. Assert NEONCLKOFF with a value of 1’b1.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release nNEONRESET.

  6. Wait for the equivalent of another approximately 10 cycles, again to compensate for clock and reset tree latencies.

  7. Deassert NEONCLKOFF. This ensures that all registers in the SIMD MPE part of the processor see the same CLK edge on exit from the reset sequence.

Use nNEONRESET to control the SIMD part of the MPE logic independently of the Cortex-A9 processor reset. Use this reset to hold the SIMD part of the MPE in a reset state so that the power to the SIMD part of the MPE can be safely switched on or off. See Table 2.2.

Debug reset

This reset initializes the debug logic in the Cortex-A9 uniprocessor, including breakpoints and watchpoints values.

To perform a debug reset, you must assert the nDBGRESET signal LOW during a few CLK cycles.

Was this page helpful? Yes No