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2.4.2. Cortex-A9 processor power control

Place holders for level-shifters and clamps are inserted around the Cortex-A9 processor to ease the implementation of different power domains.

The Cortex-A9 processor can have the following power domains:

  • a power domain for Cortex-A9 processor logic

  • a power domain for Cortex-A9 processor MPE

  • a power domain for Cortex-A9 processor RAMs.

Table 2.2 shows the power modes.

Table 2.2. Cortex-A9 processor power modes
ModeCortex-A9 processor RAM arraysCortex-A9 processor logicCortex-A9 data engineDescription
Full Run ModePowered-up

Powered-up

Powered-up

-
  ClockedClocked
Run Mode with MPE disabledPowered-upPowered-upPowered-upSee Coprocessor Access Control Register for information about disabling the MPE
 ClockedNo clock
Run Mode with MPE powered offPowered-upPowered-upPowered offThe MPE can be implemented in a separate power domain and be powered off separately
 Clocked  
StandbyPowered-up

Powered-up

Powered Up Standby modes, see Standby modes
Only wake-up logic is clocked.Clock is disabled, or powered off
DormantRetention state/voltagePowered-offPowered-offExternal wake-up event required to wake up
ShutdownPowered-offPowered-offPowered-offExternal wake-up event required to wake up

Entry to Dormant or Shutdown mode must be controlled through an external power controller.

Run mode

Run mode is the normal mode of operation, where all of the functionality of the Cortex-A9 processor is available.

Standby modes

WFI and WFE Standby modes disable most of the clocks in a processor, while keeping its logic powered up. This reduces the power drawn to the static leakage current, leaving a tiny clock power overhead requirement to enable the device to wake up.

Entry into WFI Standby mode is performed by executing the WFI instruction.

The transition from the WFI Standby mode to the Run mode is caused by:

  • An IRQ interrupt, regardless of the value of the CSPR.I bit.

  • An FIQ interrupt, regardless of the value of the CSPR.F bit.

  • An asynchronous abort, regardless of the value of the CPSR.A bit.

  • A debug event, if invasive debug is enabled and the debug event is permitted.

  • A CP15 maintenance request broadcast by other processors. This applies to the Cortex-A9 MPCore product only.

Entry into WFE Standby mode is performed by executing the WFE instruction.

The transition from the WFE Standby mode to the Run mode is caused by:

  • An IRQ interrupt, unless masked by the CPSR.I bit.

  • An FIQ interrupt, unless masked by the CPSR.F bit.

  • An asynchronous abort, unless masked by the CPSR.A bit.

  • A debug event, if invasive debug is enabled and the debug event is permitted.

  • The assertion of the EVENTI input signal.

  • The execution of an SEV instruction on any processor in the multiprocessor system. This applies to the Cortex-A9 MPCore product only.

  • A CP15 maintenance request broadcast by other processors. This applies to the Cortex-A9 MPCore product only.

The debug request can be generated by an externally generated debug request, using the EDBGRQ pin on the Cortex-A9 processor, or from a Debug Halt instruction issued to the Cortex-A9 processor through the APB debug port.

The debug channel remains active throughout a WFI instruction.

Dormant mode

Dormant mode enables the Cortex-A9 processor to be powered down, while leaving the caches powered up and maintaining their state.

The RAM blocks that must remain powered up during Dormant mode are:

  • all data RAMs associated with the cache

  • all tag RAMs associated with the cache

  • outer RAMs.

The RAM blocks that are to remain powered up must be implemented on a separate power domain.

Before entering Dormant mode, the state of the Cortex-A9 processor, excluding the contents of the RAMs that remain powered up in dormant mode, must be saved to external memory. These state saving operations must ensure that the following occur:

  • All ARM registers, including CPSR and SPSR registers are saved.

  • All system registers are saved.

  • All debug-related state must be saved.

  • A Data Synchronization Barrier instruction is executed to ensure that all state saving has completed.

  • The Cortex-A9 processor then communicates with the power controller, using the STANDBYWFI, to indicate that it is ready to enter dormant mode by performing a WFI instruction. See Communication to the power management controller for more information.

  • Before removing the power, the reset signals to the Cortex-A9 processor must be asserted by the external power control mechanism.

The external power controller triggers the transition from Dormant state to Run state. The external power controller must assert reset to the Cortex-A9 processor until the power is restored. After power is restored, the Cortex-A9 processor leaves reset and can determine that the saved state must be restored.

Shutdown mode

Shutdown mode powers down the entire device, and all state, including cache, must be saved externally by software. This state saving is performed with interrupts disabled, and finishes with a Data Synchronization Barrier operation. The Cortex-A9 processor then communicates with a power controller that the device is ready to be powered down in the same manner as when entering Dormant Mode. The processor is returned to the run state by asserting reset.

Note

You must power up the processor before performing a reset.

Communication to the power management controller

Communication between the Cortex-A9 processor and the external power management controller can be performed using the Standby signals, Cortex-A9 input clamp signals, and DBGNOPWRDWN.

Standby signals

These signals control the external power management controller.

The STANDBYWFI signal indicates that the Cortex-A9 processor is ready to enter Power Down mode. See WFE and WFI standby signals.

Cortex-A9 input signals

The external power management controller uses NEONCLAMP and CPURAMCLAMP to isolate Cortex-A9 power domains from one another before they are turned off. These signals are only meaningful if the Cortex-A9 processor implements power domain clamps. See Power management signals.

DBGNOPWRDWN

DBGNOPWRDWN is connected to the system power controller and is interpreted as a request to operate in emulate mode. In this mode, the Cortex-A9 processor and PTM are not actually powered down when requested by software or hardware handshakes. See Miscellaneous debug interface signals.

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