accurate branch and return prediction, reducing the number of incorrect instruction fetch and decode operations

the use of physically addressed caches, reducing the number of cache flushes and refills, saving energy in the system

the use of micro TLBs reduces the power consumed in translation and protection lookups for each cycle

caches that use sequential access information to reduce the number of accesses to the tag RAMs and to unnecessary accesses to data RAMs

instruction loops that are smaller than 64 bytes often complete without additional instruction cache accesses, so lowering power consumption.