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7.4.3. Cortex-A9 behavior for Normal Memory Cacheable memory regions

Depending on its configuration settings, and on the inner attributes specified in the page table descriptors, the Cortex-A9 cacheable accesses behave as follows:

SCTLR.C=0

The Cortex-A9 L1 Data Cache is not enabled. All memory accesses to Normal Memory Cacheable regions are treated as Normal Memory Non-Cacheable, without lookup and without allocation in the L1 Data Cache.

SCTLR.C=1

The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated as Non-Cacheable:

  • all pages marked as Write-Through are treated as Non-Cacheable

  • if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.

Note

ARUSER[4:0] and AWUSER[4:0] directly reflect the value of the Inner attributes and Shared attribute as defined in the corresponding page descriptor. They do not reflect how the Cortex-A9 processor interprets them, and whether the access was treated as Cacheable or not.

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