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8.1.4. AXI USER bits

The AXI USER bits encodings are as follows:

Data side read bus, ARUSERM0[6:0]

Table 8.3 shows the bit encodings for ARUSERM0[6:0]

Table 8.3. ARUSERM0[6:0] encodings
BitsNameDescription
[6]Reservedb0
[5]L2 Prefetch hint Indicates that the read access is a prefetch hint to the L2, and does not expect any data back
[4:1]Inner attributes
b0000

Strongly Ordered

b0001

Device

b0011

Normal Memory Non-Cacheable

b0110

Write-Through

b0111

Write-Back no Write-Allocate

b1111

Write-Back Write-Allocate.

[0]Shared bit
0

Nonshared

1

Shared.


Instruction side read bus, ARUSERM1[6:0]

Table 8.4 shows the bit encodings for ARUSERM1[6:0].

Table 8.4. ARUSERM1[6:0] encodings
BitsNameDescription
[6]Reservedb0
[5]Reservedb0
[4:1]Inner attributes
b0000

Strongly Ordered

b0001

Device

b0011

Normal Memory Non-Cacheable

b0110

Write-Through

b0111

Write-Back no Write-Allocate

b1111

Write-Back Write-Allocate.

[0]Shared bit
0

Nonshared

1

Shared.


Data side write bus, AWUSERM0[8:0]

Table 8.5 shows the bit encodings for AWUSERM0[8:0].

Table 8.5. AWUSERM0[8:0] encodings
BitsNameDescription
[8]Early BRESP Enable bitIndicates that the L2 slave can send an early BRESP answer to the write request. See Early BRESP.
[7]Write full line of zeros bitIndicates that the access is an entire cache line write full of zeros. See Write full line of zeros.
[6]Clean evictionIndicates that the write access is the eviction of a clean cache line.
[5]L1 evictionIndicates that the write access is a cache line eviction from the L1.
[4:1]Inner attributes
b0000

Strongly Ordered

b0001

Device

b0011

Normal Memory Non-Cacheable

b0110

Write-Through

b0111

Write-Back no Write-Allocate

b1111

Write-Back Write-Allocate.

[0]Shared bit
0

Nonshared

1

Shared.


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