You copied the Doc URL to your clipboard.

8.1.1. Cortex-A9 L2 interface

The Cortex-A9 L2 interface consists of two 64-bit wide AXI bus masters:

  • M0 is the data side bus

  • M1 is the instruction side bus and has no write channels.

Table 8.1 shows the AXI master 0 interface attributes.

Table 8.1. AXI master 0 interface attributes
AttributeFormat
Write issuing capability

12, including:

  • eight noncacheable writes

  • four evictions.

Read issuing capability

10, including:

  • six linefill reads.

  • four noncacheable read

Combined issuing capability22
Write ID capability2
Write interleave capability1
Write ID width2
Read ID capability3
Read ID width2

Table 8.2 shows the AXI master 1 interface attributes.

Table 8.2. AXI master 1 interface attributes
AttributeFormat
Write issuing capability

None

Read issuing capability

4 instruction reads

Combined issuing capability4
Write ID capabilityNone
Write interleave capabilityNone
Write ID widthNone
Read ID capability4
Read ID width2

Note

The numbers in Table 8.1 and Table 8.2 are the theoretical maximums for the Cortex-A9 MPCore processor. A typical system is unlikely to reach these numbers. ARM recommends that you perform profiling to tailor your system resources appropriately for optimum performance.

The AXI protocol and meaning of each AXI signal are not described in this document. For more information see AMBA AXI Protocol v1.0 Specification.

Was this page helpful? Yes No