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6.1. About the MMU

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory.

The Virtual Memory System Architecture version 7 (VMSAv7) features include the following:

  • page table entries that support 4KB, 64KB, 1MB, and 16MB

  • 16 domains

  • global and address space identifiers to remove the requirement for context switch TLB flushes

  • extended permissions check capability.

See the ARM Architecture Reference Manual for a full architectural description of the VMSAv7.

The processor implements the ARMv7-A MMU enhanced with Security Extensions and multiprocessor extensions to provide address translation and access permission checks. The MMU controls table walk hardware that accesses translation tables in main memory. The MMU enables fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes.

Note

In VMSAv7 first level descriptor formats page table base address bit [9] is implementation-defined. In Cortex-A9 processor designs this bit is unused.

The MMU features include the following:

  • Instruction side micro TLB

    • hardware configurable 32 or 64 fully associative entries.

  • Data side micro TLB

    • 32 fully associative entries.

  • Unified main TLB

    • 2-way associative:

      2x32 entry TLB

      for the 64-entry TLB.

      2x64 entry TLB

      for the 128-entry TLB.

      2x128 entry TLB

      for the 256-entry TLB.

      2x256 entry TLB

      for the 512-entry TLB.

    • 4 lockable entries using the lock-by-entry model.

    • supports hardware page table walks to perform lookups in the L1 data cache.

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