The main TLB catches the misses from the micro TLBs. It also provides a centralized source for lockable translation entries.
Accesses to the main TLB take a variable number of cycles, according to competing requests from each of the micro TLBs and other implementation-dependent factors. Entries in the lockable region of the main TLB are lockable at the granularity of a single entry. As long as the lockable region does not contain any locked entries, it can be allocated with non-locked entries to increase overall main TLB storage size.
The main TLB is implemented as a combination of:
a fully-associative, lockable array of four elements
a 2-way associative structure of 2x32, 2x64,2x128 or 2x256 entries.
Each TLB entry contains a virtual address, a page size, a physical address, and a set of memory properties. Each is marked as being associated with a particular application space, or as global for all application spaces. CONTEXIDR determines the selected application space. A TLB entry matches if bits [31:N] of the modified virtual address match, where N is log2 of the page size for the TLB entry. It is either marked as global, or the ASID matched the current ASID.
A TLB entry matches when these conditions are true:
its virtual address matches that of the requested address
its Non-secure TLB ID (NSTID) matches the Secure or Non-secure state of the MMU request
its ASID matches the current ASID or is global.
The operating system must ensure that, at most, one TLB entry matches at any time.
Supersections, sections, and large pages are supported to permit mapping of a large region of memory while using only a single entry in a TLB. If no mapping for an address is found in the TLB, then the translation table is automatically read by hardware and a mapping is placed in the TLB.
The TLB supports the TLB lock-by-entry model as described in the ARM Architecture Reference Manual. See TLB lockdown operations for more information.