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11.3. PMU management registers

The PMU management registers define the standardized set of registers that is implemented by all CoreSight components. This section describes these registers.

You can access these registers through the APB interface only, using the offset listed in Table 11.2 when PADDRDBG[12]=1.

Table 11.2 shows the contents of the management registers for the Cortex-A9 PMU.

Table 11.2. PMU management registers
Register numberOffsetNameTypeDescription
9600xF00PMITCTRLRAZ/WIIntegration Mode Control Register
961-9990xF04-0xF9C-RAZReserved
10000xFA0PMCLAIMSETRWClaim Tag Set Register
10010xFA4PMCLAIMCLRRWClaim Tag Clear Register
1002-10030xFA8-0xFBC-RAZReserved
10040xFB0PMLARWOLock Access Register
10050xFB4PMLSRROLock Status Register
10060xFB8PMAUTHSTATUSROAuthentication Status Register
1007-10090xFBC-0xFC4-RAZReserved
10100xFC8PMDEVIDRAZ/WIDevice ID Register
10110xFCCPMDEVTYPERODevice Type Register
1012-10190xFD0-0xFECPMPIDROSee Peripheral Identification Registers
1020- 10230xFF0-0xFFCPMCIDROSee Component Identification Registers

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