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11.2. PMU register summary

You can access the PMU counters, and their associated control registers:

  • through the internal CP15 interface

  • through the APB, using the relevant offset when PADDRDBG[12]=1.

Table 11.1 gives a summary of the Cortex-A9 PMU registers.

Table 11.1. PMU register summary
Register numberOffsetCRnOp1CRmOp2NameTypeDescription
00x000c90c132PMXEVCNTR0RWEvent Count Register, see the ARM Architecture Reference Manual
10x004c90c132PMXEVCNTR1RW
20x008c90c132PMXEVCNTR2RW
30x00Cc90c132PMXEVCNTR3RW
40x010c90c132PMXEVCNTR4RW
50x014c90c132PMXEVCNTR5RW
6-300x018- 0x078------Reserved
310x07Cc90c130PMCCNTRRWCycle Count Register, see the ARM Architecture Reference Manual
32-2550x080-0x3FC------Reserved
2560x400c90c131PMXEVTYPER0RWEvent Type Selection Register, see the ARM Architecture Reference Manual
2570x404c90c131PMXEVTYPER1RW
2580x408c90c131PMXEVTYPER2RW
2590x40Cc90c131PMXEVTYPER3RW
2600x410c90c131PMXEVTYPER4RW
2610x414c90c131PMXEVTYPER5RW
262-7670x418-0xBFC------Reserved
7680xC00c90c121PMCNTENSETRWCount Enable Set Register, see the ARM Architecture Reference Manual
769-7750xC04-0xC1C------Reserved
7760xC20c90c122PMCNTENCLRRWCount Enable Clear Register, see the ARM Architecture Reference Manual
777-7830xC24-0xC3C------Reserved
7840xC40c90c141PMINTENSETRWInterrupt Enable Set Register, see the ARM Architecture Reference Manual
785-7910xC44-0xC5C------Reserved
7920xC60c90c142PMINTENCLRRWInterrupt Enable Clear Register, see the ARM Architecture Reference Manual
793-7990xC64-0xC7C------Reserved
8000xC80c90c123PMOVSRRWOverflow Flag Status Register, see the ARM Architecture Reference Manual
801-8070xC84-0xC7C------Reserved
8080xCA0c90c124PMSWINCWOSoftware Increment Register, see the ARM Architecture Reference Manual
809-8310xCA4-0xCFC------Reserved
832-895--------
8960xE00------Reserved
8970xE04c90c120PMCRRWPerformance Monitor Control Register, see the ARM Architecture Reference Manual
898

0xE08

c90c140PMUSERENR

RW[a]

User Enable Register, see the ARM Architecture Reference Manual
 -c90c125PMSELRRWEvent Counter Select Register, see the ARM Architecture Reference Manual
899-9590xE0C-0xEFC------Reserved
960-10230xF00-0xFFC----PMU Management Registers-PMU management registers

[a] Read-only in User mode.


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