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9.3.5. PLE Program New Channel operation

The PLE Program new channel operation characteristics are:

Purpose

Programs a new memory region to preload into L2 memory.

Figure 9.1 shows the <Rt>. and <Rt2> bit assignments for PLE program new channel operations. Rt is the register that contains the Base address. Rt2 is the register that contains the length, stride, and number of blocks.

Figure 9.1. Program new channel operation bit assignments

Figure 9.1. Program new channel operation bit assignments

Table 9.1 shows the PLE program new channel operation bit assignments.

Table 9.1. PLE program new channel operation bit assignments
BitsNameDescription
[63:34]Base address (VA)This is the 32-bit Base Virtual Address of the first block of memory to preload. The address is aligned on a word boundary. That is, bits [33:32] are RAZ/WI.
[33:32]-RAZ/WI
[31:18]Length

Specifies the length of the block to preload.

Length is encoded as word multiples. The range is from 14’b0000000000, a single word block, to 14’b11111111111111, a 16K word block.

[17:10]Stride

Indicates the preload stride between blocks. The preload stride is the difference between the start address of two blocks. The stride is encoded as a word multiple. The range is from 8’b00000000, contiguous blocks, to 8’b11111111, prefetch blocks every 256 words.

[9:2]Number of blocks

Specifies the number of blocks to preload.

Values range from 8’b00000000, indicating a single block preload, to 8’b11111111 indicating 256 blocks.

[1:0]-RAZ/WI

To program a new channel operation, use the MCRR operation:

MCRR p15, 0, <Rt>,<Rt2> c11; Program new PLE channel

Note

A newly programmed PLE entry is written to the PLE FIFO if the FIFO has available entries. In cases of FIFO overflow, the instruction silently fails, and the FIFO Overflow event signal is asserted. See Preload events in Table 11.6. See PLE FIFO Status Register.

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