The CCSIDR characteristics are:
Provides information about the architecture of the caches selected by CSSELR.
- Usage constraints
The CCSIDR is:
only accessible in privileged modes
common to the Secure and Non-secure states.
Available in all configurations.
See the register summary in Table 4.2.
Figure 4.5 shows the CCSIDR bit assignments.
Table 4.32 shows how the CSSIDR bit assignments.
Indicates support available for Write-Through:
Indicates support available for Write-Back:
Indicates support available for Read-Allocation:
Indicates support available for Write-Allocation:
Indicates number of sets:
Indicates number of ways:
Indicates number of words:
To access the CCSIDR, read the CP15 register with:
MRC p15, 1, <Rd>, c0, c0, 0; Read current Cache Size Identification Register
If the CSSELR reads the instruction cache values, then bits [31:28] are b0010.
If the CSSELR reads the data cache values, then bits [31:28] are b0111. See Cache Size Selection Register.