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4.3.5. Cache Size Identification Register

The CCSIDR characteristics are:

Purpose

Provides information about the architecture of the caches selected by CSSELR.

Usage constraints

The CCSIDR is:

  • only accessible in privileged modes

  • common to the Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.5 shows the CCSIDR bit assignments.

Figure 4.5. CCSIDR bit assignments

Figure 4.5. CCSIDR bit assignments

Table 4.32 shows how the CSSIDR bit assignments.

Table 4.32. CCSIDR bit assignments
BitsNameFunction

[31]

WT

Indicates support available for Write-Through:

0

Write-Through support not available

1

Write-Through support available.

[30]

WB

Indicates support available for Write-Back:

0

Write-Back support not available

1

Write-Back support available.

[29]

RA

Indicates support available for Read-Allocation:

0

Read-Allocation support not available

1

Read-Allocation support available.

[28]

WA

Indicates support available for Write-Allocation:

0

Write-Allocation support not available

1

Write-Allocation support available.

[27:13]

NumSets

Indicates number of sets:

0x7F

16KB cache size

0xFF

32KB cache size

0x1FF

64KB cache size.

[12:3]

Associativity

Indicates number of ways:

b0000000011

Four ways.

[2:0]

LineSize

Indicates number of words:

b001

Eight words per line.


To access the CCSIDR, read the CP15 register with:

MRC p15, 1, <Rd>, c0, c0, 0; Read current Cache Size Identification Register

If the CSSELR reads the instruction cache values, then bits [31:28] are b0010.

If the CSSELR reads the data cache values, then bits [31:28] are b0111. See Cache Size Selection Register.

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