You copied the Doc URL to your clipboard.

4.3.16. PLE ID Register

The PLEIDR characteristics are:

Purpose

Indicates whether the PLE is present or not and the size of its FIFO.

Usage constraints

The PLEIDR is:

  • common to Secure and Non-secure states

  • accessible in User and privileged modes, regardless of any configuration bit.

Configurations

Available in all Cortex-A9 configurations regardless of whether a PLE is present or not.

Attributes

Figure 4.15 shows the PLEIDR bit assignments.

Figure 4.15. PLEIDR bit assignments

Figure 4.15. PLEIDR bit assignments

Table 4.42 shows the PLEIDR bit assignments.

Table 4.42. PLEIDR bit assignments
BitsNameFunction
[31:21]--
[20:16]PLE FIFO size

Permitted values are:

b00000

indicates the PLE is not present

b00100

indicates a PLE is present with a FIFO size of 4 entries

b01000

indicates a PLE is present with a FIFO size of 8 entries

b10000

indicates a PLE is present with a FIFO size of 16 entries.

[15:1]-RAZ.
[0]-A value of 1 indicates that the Preload Engine is present in the given configuration.

To access the PLEIDR, read the CP15 register with:

MRC p15, 0, <Rt>, c11, c0, 0; Read PLEIDR
Was this page helpful? Yes No