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4.3.2. TLB Type Register

The TLBTR characteristics are:

Purpose

Returns the number of lockable entries for the TLB.

Usage constraints

The TLBTR is:

  • common to the Secure and Non-secure states

  • only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.2 shows the TLBTR bit assignments.

Figure 4.2. TLBTR bit assignments

Figure 4.2. TLBTR bit assignments

Table 4.29 shows the TLBTR bit assignments.

Table 4.29. TLBTR bit assignments
BitsNameFunction
[31:24]SBZ -
[23:16]ILsize

Specifies the number of instruction TLB lockable entries.

For the Cortex-A9 processor, this is 0.

[15:8]DLsize

Specifies the number of unified or data TLB lockable entries.

For the Cortex-A9 processor, this is 4.

[7:3]SBZ or UNP-
[2:1]TLB_size
00

TLB has 64 entries

01

TLB has 128 entries

10

TLB has 256 entries

11

TLB has 512 entries.

[0]nU

Specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs.

0

The Cortex-A9 processor has a unified TLB.


To access the TLBTR, read the CP15 register with:

MRC p15,0,<Rd>,c0,c0,3; returns TLB details
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