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9.7.3. Debug access port register descriptions

This section gives a detailed description of each of the debug port registers. Each description states whether the register is implemented for the JTAG-DP and for the SW-DP and shows any differences in the implementation.

Abort Register, ABORT

The Abort Register is always present on all debug port implementations. Its main purpose is to force a DAP abort. On a SW-DP, it is also used to clear error and sticky flag conditions.

JTAG-DP

It is at address 0x0 when the Instruction Register (IR) contains ABORT.

SW-DP

It is at address 0x0 on write operations when the APnDP bit =1, see Key to illustrations of operations. Access to the Abort Register is not affected by the value of the CTRLSEL bit in the Select Register.

It is:

  • A write-only register.

  • Always accessible and returns an OK response if a valid transaction is received.

    Abort Register accesses always complete on the first attempt.

Figure 9.21 shows the Abort Register bit assignments.

Figure 9.21. Abort Register bit assignments

Figure 9.21. Abort Register bit assignments

Table 9.14 shows the Abort Register bit assignments.

Abort Register bit assignments
BitsFunctionDescription
[31:5]-Reserved, SBZ.
[4][1]ORUNERRCLR[1]Write b1 to this bit to clear the STICKYORUN overrun error flag[2].
[3][1]WDERRCLR[1]Write b1 to this bit to clear the WDATAERR write data error flag[2].
[2][1]STKERRCLR[1]Write b1 to this bit to clear the STICKYERR sticky error flag[2].
[1][1]STKCMPCLR[1]Write b1 to this bit to clear the STICKYCMP sticky compare flag[2].
[0]DAPABORT

Write b1 to this bit to generate a DAP abort. This aborts the current access port transaction.

This must only be done if the debugger has received WAIT responses over an extended period.

[1] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, SBZ.

[2] In the Control/Status register.

DP Aborts

Writing b1 to bit [0] of the Abort Register generates a debug port abort, causing the current AP transaction to abort. This also terminates the Transaction Counter, if it was active.

From a software perspective, this is a fatal operation. It discards any outstanding and pending transactions and leaves the access port in an unknown state. However, on a SW-DP, the sticky error bits are not cleared.

You use this function only in extreme cases, where debug host software has observed stalled target hardware for an extended period. Stalled target hardware is indicated by WAIT responses.

After a debug port abort is requested, new transactions can be accepted by the debug port. However, an access port access to the access port that was aborted can result in more WAIT responses. Other access ports can be accessed, however, the state of the system might make it impossible to continue with debug.

On a JTAG-DP, for the Abort Register:

  • bit [0], DAPABORT, is the only bit that is defined

  • the effect of writing any value other than 0x00000001 is Unpredictable.

Clearing error and sticky compare flags, SW-DP only

When a debugger, connected to a SW-DP, checks the Control/Status Register and finds that an error flag is set, or that the sticky compare flag is set, it must write to the Abort register to clear the error or sticky compare flag. Table 9.14 lists the flags that might be set in the Control/Status Register and shows which bit of the Abort register is used to clear each of the flags. You can use a single write of the Abort Register to clear multiple flags, if this is necessary.

After clearing the flag, you might have to access the debug port and access port registers to find what caused the flag to be set. Typically:

  • For the STICKYCMP or STICKYERR flag, you must find which location was accessed to cause the flag to be set.

  • For the WDATAERR flag, after clearing the flag you must resend the data that was corrupted.

  • For the STICKYORUN flag, you must find which debug port or access port transaction caused the overflow. You then have to repeat your transactions from that point.

Identification Code Register, IDCODE

The Identification Code Register is always present on all debug port implementations. It provides identification information about the ARM Debug Interface.

JTAG-DP

It is accessed using its own scan chain.

SW-DP

It is at address 0b00 on read operations when the APnDP bit =1. Access to the Identification Code Register is not affected by the value of the CTRLSEL bit in the Select Register.

It is:

  • a read-only register

  • always accessible.

Figure 9.22 shows the Identification Code Register bit assignments.

Figure 9.22. Identification Code Register bit assignments

Figure 9.22. Identification Code Register bit
assignments

Table 9.15 shows the Identification Code Register bit assignments.

Identification Code Register bit assignments
BitsFunctionDescription
[31:28]Version

Version code:

JTAG-DP

0x3

SW-DP

0x2

[27:12]PARTNO

Part Number for the debug port. Current ARM-designed debug ports have the following PARTNO values:

JTAG-DP

0xBA00

SW-DP

0xBA10

[11:1]MANUFACTURER

JEDEC Manufacturer ID, an 11-bit JEDEC code that identifies the manufacturer of the device. See JEDEC Manufacturer ID. The ARM default value for this field, shown in Figure 9.22, is 0x23B.

[0]-Always 0b1.
JEDEC Manufacturer ID

This code is also described as the JEP-106 manufacturer identification code and can be subdivided into two fields, as shown in Table 9.16.

JEDEC JEP-106 manufacturer ID code, with ARM Limited values
JEP-106 fieldBits[1]ARM Limited registered value
Continuation code4 bits, [11:8]b0100, 0x4
Identity code7 bits, [7:1]b0111011, 0x3B

[1] Field width, in bits, and the corresponding bits in the Identification Code Register.

JDEC codes are assigned by the JEDEC Solid State Technology Association, see JEP106M, Standard Manufacture’s Identification Code.

Control/Status Register, CTRL/STAT

The Control/Status Register is always present on all debug port implementations. It provides control of the debug port and status information about the debug port.

JTAG-DP

It is at address 0x4 when the Instruction Register (IR) contains DPACC.

SW-DP

It is at address 0b01 on read and write operations when the APnDP bit =1 and the CTRLSEL bit in the Select Register is set to b0. For information about the CTRLSEL bit see AP Select Register, SELECT.

It is a read-write register, in which some bits have different access rights. It is implementation-defined whether some fields in the register are supported. Table 9.17 shows which fields are required in all implementations.

Figure 9.23 shows the Control/Status Register bit assignments.

Figure 9.23. Control/Status Register bit assignments

Figure 9.23. Control/Status Register bit assignments

Table 9.17 shows the Control/Status Register bit assignments.

Control/Status Register bit assignments
BitsAccessFunctionDescription
[31]ROCSYSPWRUPACKSystem power-up acknowledge.
[30]R/WCSYSPWRUPREQSystem power-up request. After a reset this bit is LOW (0).
[29]ROCDBGPWRUPACK Debug power-up acknowledge.
[28]R/WCDBGPWRUPREQ Debug power-up request. After a reset this bit is LOW (0).
[27]ROCDBGRSTACKDebug reset acknowledge.
[26]R/WCDBGRSTREQ

Debug reset request. After a reset this bit is LOW (0).

[25:24]--Reserved, RAZ/SBZP.
[21:12]R/WTRNCNT

Transaction counter. After a reset the value of this field is Unpredictable.

[11:8]R/WMASKLANE

Indicates the bytes to be masked in pushed compare and pushed verify operations. See MASKLANE and the bit masking of the pushed compare and pushed verify operations.

After a reset the value of this field is Unpredictable.

[7]RO[1]WDATAERR[1]

This bit is set to 1 if a Write Data Error occurs. It is set if:

  • there is a a parity or framing error on the data phase of a write

  • a write that has been accepted by the debug port is then discarded without being submitted to the access port.

This bit can only be cleared by writing b1 to the WDERRCLR field of the Abort Register, see Abort Register, ABORT.

After a power-on reset this bit is LOW (0).

[6]RO[1]READOK[1]

This bit is set to 1 if the response to a previous access port or RDBUFF was OK. It is cleared to 0 if the response was not OK.

This flag always indicates the response to the last access port read access.

After a power-on reset this bit is LOW (0).

[5]RO[2]STICKYERR

This bit is set to 1 when the processor receives a bus error on the system AHB-Lite bus.

When STICKYERR is set, no transaction is passed from the JTAG or SW interfaces to the debug AHB system bus. Any read that is performed when STICKYERR is set results in data that is Unpredictable.

To clear this bit:

On a JTAG-DP

Write b1 to this bit of this register.

On a SW-DP

Write b1 to the STKERRCLR field of the Abort Register, see Abort Register, ABORT.

After a power-on reset this bit is LOW (0).

[4]RO[2]STICKYCMP

This bit is set to 1 when a match occurs on a pushed compare or a pushed verify operation. To clear this bit:

On a JTAG-DP

Write b1 to this bit of this register.

On a SW-DP

Write b1 to the STKCMPCLR field of the Abort Register, see Abort Register, ABORT.

After a power-on reset this bit is LOW (0).

[3:2]R/WTRNMODE

This field sets the transfer mode for access port operations, see Transfer mode (TRNMODE), bits [3:2].

After a power-on reset the value of this field is Unpredictable.

[1]RO[2]STICKYORUN

If overrun detection is enabled (see bit [0] of this register), this bit is set to 1 when an overrun occurs. To clear this bit:

On a JTAG-DP

Write b1 to this bit of this register.

On a SW-DP

Write b1 to the ORUNERRCLR field of the Abort Register, see Abort Register, ABORT.

After a power-on reset this bit is LOW (0).

[0]R/WORUNDETECT

This bit is set to b1 to enable overrun detection.

After a reset this bit is Low (0).

[1] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, RAZ/SBZP.

[2] RO on SW-DP. On a JTAG-DP, this bit can be read normally. Writing b1 to this bit clears the bit to b0.

MASKLANE and the bit masking of the pushed compare and pushed verify operations

The MASKLANE field, bits [11:8] of the CTRL/STAT Register, is only relevant if the Transfer Mode is set to pushed verify or pushed compare operation, see Transfer mode (TRNMODE), bits [3:2].

In the pushed operations, the word supplied in an access port write transaction is compared with the current value of the target access port address. The MASKLANE field lets you specify that the comparison is made using only certain bytes of the values. Each bit of the MASKLANE field corresponds to one byte of the access port values. Therefore, each bit is said to control one byte lane of the compare operation.

Table 9.18 shows how the bits of MASKLANE control the comparison masking.

Control of pushed operation comparisons by MASKLANE
MASKLANE[1]MeaningMask used for comparisons[2]
b1XXXInclude byte lane 3 in comparisons.0xFF------
bX1XXInclude byte lane 2 in comparisons.0x--FF----
bXX1XInclude byte lane 1 in comparisons.0x----FF--
bXXX1Include byte lane 0 in comparisons.0x------FF

[1] Bits [11:8] of the CTRL/STAT Register.

[2] Bytes of the mask shown as -- are determined by the other bits of MASKLANE.

Transfer mode (TRNMODE), bits [3:2]

This field sets the transfer mode for access port operations. Table 9.19 lists the permitted values of this field and their meanings.

Transfer Mode bit definitions
TRNMODE[1]AP Transfer mode
b00Normal operation
b01Pushed verify operation
b10Pushed compare operation
b11Reserved

[1] Bits [3:2] of the CTRL/STAT Register.

In normal operation, access port transactions are passed to the access port for processing.

In pushed verify and pushed compare operations, the debug port compares the value supplied in the access port transaction with the value held in the target access port address.

AP Select Register, SELECT

The AP Select Register is always present on all debug port implementations. Its main purpose is to select the current Access Port (AP) and the active four-word register window in that access port. On a SW-DP, it also selects the Debug Port address bank.

JTAG-DP

It is at address 0x8 when the Instruction Register (IR) contains DPACC and is a read/write register.

SW-DP

It is at address 0b10 on write operations when the APnDP bit =1 and is a write-only register. Access to the AP Select Register is not affected by the value of the CTRLSEL bit.

Figure 9.24 shows the AP Select Register bit assignments.

Figure 9.24. AP Select Register bit assignments

Figure 9.24. AP Select Register bit assignments

Table 9.20 shows the AP Select Register bit assignments.

AP Select Register bit assignments
BitsFunctionDescription
[31:24]APSEL

Selects current access port.

Note

Because the processor has only one access port, APSEL must be 8'b00000000.

The reset value of this field is Unpredictable.[1]

[23:8]-Reserved. SBZ/RAZ[1].
[7:4]APBANKSEL

Selects the active 4-word register window on the current access port.

The reset value of this field is Unpredictable.[1]

[3:1]-Reserved. SBZ/RAZ[1].
[0]CTRLSEL[2]

SW-DP Debug Port address bank select, see CTRLSEL, SW-DP only.

After a reset this field is b0. However the register is WO so you cannot read this value.

[1] On a SW-DP the register is write-only and therefore you cannot read the field value.

[2] Implemented on SW-DP only. On a JTAG-DP this bit is Reserved, SBZ/RAZ.

If APSEL is set to a non-existent access port, all access port transactions return zero on reads and are ignored on writes.

CTRLSEL, SW-DP only

The CTRLSEL field, bit [0], controls which debug port register is selected at address b01 on a SW-DP. Table 9.21 shows the meaning of the different values of CTRLSEL.

CTRLSEL field bit definitions
CTRLSEL[1]DP Register at address b01
0CTRL/STAT, see Control/Status Register, CTRL/STAT
1WCR, see Wire Control Register, WCR (SW-DP only)

[1] Bit [0] of the SELECT Register.

Read Buffer, RDBUFF

The 32-bit Read Buffer is always present on all debug port implementations. However, there are significant differences in its implementation on JTAG and SW Debug Ports.

JTAG-DP

It is at address 0xC when the Instruction Register (IR) contains DPACC and is a Read-as-zero, Writes ignored (Reserved) register.

SW-DP

It is at address 0xC on read operations when the APnDP bit =1 and is a read-only register. Access to the Read Buffer is not affected by the value of the CTRLSEL bit in the SELECT Register.

Read Buffer implementation and use on a JTAG-DP

On a JTAG-DP, the Read Buffer always reads as zero. Writes to the Read Buffer address are ignored.

The Read Buffer is architecturally defined to provide a debug port read operation that does not have any side effects. This means that a debugger can insert a debug port read of the Read Buffer at the end of a sequence of operations, to return the final Read Result and ACK values.

Read Buffer implementation and use on a SW-DP

On a SW-DP, performing a read of the Read Buffer captures data from the access port, presented as the result of a previous read, without initiating a new access port transaction. This means that reading the Read Buffer returns the result of the last access port read access, without generating a new AP access.

After you have read the Read Buffer, its contents are no longer valid. The result of a second read of the Read Buffer is Unpredictable.

If you require the value from an access port register read, that read must be followed by one of:

  • A second access port register read. You can read the Control/Status Register (CSW) if you want to ensure that this second read has no side effects.

  • A read of the DP Read Buffer.

This second access, to the access port or the debug port depending on which option you used, stalls until the result of the original access port read is available.

Wire Control Register, WCR (SW-DP only)

The Wire Control Register is always present on any SW-DP implementation. Its purpose is to select the operating mode of the physical serial port connection to the SW-DP.

It is a read/write register at address 0b01 on read and write operations when the CTRLSEL bit in the Select Register is set to b1. For information about the CTRLSEL bit see AP Select Register, SELECT.

Note

When the CTRLSEL bit is set to b1, to enable access to the WCR, the DP Control/Status Register is not accessible.

Many features of the Wire Control Register are implementation-defined.

Figure 9.25 shows the Wire Control Register bit assignments.

Figure 9.25. Wire Control Register bit assignments

Figure 9.25. Wire Control Register bit assignments

Table 9.22 shows the Wire Control Register bit assignments.

Wire Control Register bit assignments
BitsFunctionDescription
[31:10]-Reserved. SBZ/RAZ.
[9:8]TURNROUND

Turnaround tristate period, see Turnaround tristate period, TURNROUND, bits [9:8].

After a reset this field is b00.

[7:6]WIREMODE

Identifies the operating mode for the wire connection to the debug port, see Wire operating mode, WIREMODE, bits [7:6].

After a reset this field is b01.

[5:3]-Reserved. SBZ/RAZ.
[2:0]PRESCALERReserved. SBZ/RAZ.
Turnaround tristate period, TURNROUND, bits [9:8]

This field defines the turnaround tristate period. This turnaround period allows for pad delays when using a high sample clock frequency. Table 9.23 lists the possible values of this field and their meanings.

Turnaround tristate period field bit definitions
TURNROUND[1]Turnaround tri-state period
b001 sample period
b012 sample periods
b103 sample periods
b114 sample periods

[1] Bits [9:8] of the WCR Register.

Wire operating mode, WIREMODE, bits [7:6]

This field identifies SW-DP as operating in Synchronous mode only.

This field is required. Table 9.24 lists the possible values of the field and their meanings.

Wire operating mode bit definitions
WIREMODE[1]Wire operating mode
b00Reserved
b01Synchronous (no oversampling)
b1XReserved

[1] Bits [7:6] of the WCR Register.

Read Resend Register, RESEND (SW-DP only)

The Read Resend Register is always present on any SW-DP implementation. Its purpose is to enable the read data to be recovered from a corrupted debugger transfer, without repeating the original AP transfer.

It is a 32-bit read-only register at address 0b10 on read operations. Access to the Read Resend Register is not affected by the value of the CTRLSEL bit in the SELECT Register.

Performing a read to the RESEND register does not capture new data from the access port. It returns the value that was returned by the last AP read or DP RDBUFF read.

Reading the RESEND register enables the read data to be recovered from a corrupted transfer without having to re-issue the original read request or generate a new DAP or system level access.

The RESEND register can be accessed multiple times. It always returns the same value until a new access is made to the DP RDBUFF register or to an access port register.

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