There are five physical DR registers:
the BYPASS and IDCODE Registers, as defined by the IEEE 1149.1 standard
the DPACC and APACC Access Registers
an ABORT Register, used to abort a transaction.
There is a scan chain associated with each of these registers. As described in IR scan chain and IR instructions, the value in the IR register determines which of these scan chains is connected to the TDI and TDO signals.
Device identification. The Device ID Code value enables a debugger to identify the debug port to which it is connected. Different debug ports have different Device ID Codes, so that a debugger can make this distinction.
This is the JTAG-DP implementation of the Identification Code Register, see Identification Code Register, IDCODE.
- Operating mode
When the IDCODE instruction is the current instruction in the IR, the shift section of the Device ID Code Register is selected as the serial path between TDI and TDO:
in the Capture-DR state, the 32-bit device ID code is loaded into this shift section
in the Shift-DR state, this data is shifted out, least significant bit first
the shifted-in data is ignored at the Update-DR state.
Figure 9.6 shows the bit order of the Device ID Code Register.
For this processor:
Version, bit [31:28], is set to 3
Part number, bit [27:12], is set to
Manufacturer ID, bit [11:1], is set to
Reserved, bit , is set to 1.
See Table 9.15 for more information.
The DPACC and APACC scan chains have the same format.
Initiate a debug port or access port access, to access a debug port or access port register. The DPACC and APACC are used for read and write accesses to registers:
- Operating mode
When the DPACC or APACC instruction is the current instruction in the IR, the shift section of the DP Access Register or AP Access Register is selected as the serial path between TDI and TDO:
In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Only two ACK responses are implemented. These are summarized in Table 9.3.
DPACC and APACC ACK responses Response ACK[2:0] encoding See OK/FAULT b010 OK/FAULT response to a DPACC or APACC access WAIT b001 WAIT response to a DPACC or APACC access
All other ACC encodings are Reserved.
In the Shift-DR state, this data is shifted out, least significant bit first. As shown in Figure 9.7, the first three bits of data shifted out are ACK[2:0] and, therefore, you can check the ACK response without shifting out all of the returned data, see WAIT response to a DPACC or APACC access.
As the returned data is shifted out to TDO, new data is shifted in from TDI. This is described in OK/FAULT response to a DPACC or APACC access.
Operation in the Update-DR depends on whether the ACK[2:0] response was OK/FAULT or WAIT. The two cases are described in:
Figure 9.7 shows the bit order of the DP and AP Access Registers.
If the response indicated by ACK[2:0] is OK/FAULT, the previous transaction has completed. The response code does not show whether the transaction completed successfully or was faulted. You must read the CTRL/STAT register to find whether the transaction was successful, see Control/Status Register, CTRL/STAT:
If the previous transaction was a read that completed successfully, then the captured ReadResult[31:0] is the requested register value. This result is shifted out as Data[34:3].
If the previous transaction was a write, or a read that did not complete successfully, the captured ReadResult[31:0] is Unpredictable. If Data[34:3] is shifted out it must be discarded.
The values shifted into the scan chain form a request to read or write a register:
if the current IR instruction is DPACC, TDI and TDO connect to the DPACC scan chain and the request is to read or write a DP register
if the current IR instruction is APACC, TDI and TDO connect to the APACC scan chain and the request is to read or write an AP register.
In either case:
If RnW is shifted in as 0, the request is to write the value in DATAIN[31:0] to the addressed register.
If RnW is shifted in as 1, the request is to read the value of the addressed register. The value in DATAIN[31:0] is ignored. You must read the scan chain again to obtain the value read from the register.
The required register is addressed:
In the case of a DPACC access, to read a debug port register, by the value shifted into A[3:2]. See Table 9.12 for the addressing details.
In the case of a APACC access, to read an access port register, by the combination of:
the value shifted into A[3:2]
the current value of the SELECT register in the DP, see AP Select Register, SELECT.
Register accesses can be pipelined, because a single DPACC or APACC scan can return the result of the previous read operation at the same time as requesting another register access. At the end of a sequence of pipelined register reads, you can read the DP RDBUFF Register to return the result of the final register read. Reading the DP RDBUFF Register is benign, that is, it has no effect on the operation of the JTAG, see Read Buffer, RDBUFF. The section Target response summary gives more information about how one DPACC or APACC scan returns the result from the previous scan.
If the current IR instruction is APACC, causing an APACC access:
If any sticky flag is set in the DP CTRL/STAT Register, the transaction is discarded. The next scan returns an OK/FAULT response immediately. For more information see Sticky flags and debug port error responses and Control/Status Register, CTRL/STAT.
If pushed compare or pushed verify operations are enabled then the scanned-in value of RnW must be 0, otherwise behavior is Unpredictable. On Update-DR, a read request is issued and the returned value compared against DATAIN[31:0]. The STICKYCMP flag in the DP CTRL/STAT register is updated based on this comparison. For more information see Pushed compare and pushed verify operations. Pushed operations are enabled using the TRNMODE field of the DP CTRL/STAT register, see Control/Status Register, CTRL/STAT for more information.
The AP access does not complete until the access port signals it as completed. For example, if you access a Memory Access Port (AHB-AP), the access might cause an access to a memory system connected to the AHB-AP. In this case, the access does not complete until the memory system signals to the AHB-AP that the memory access has completed.
A WAIT response indicates that the previous transaction has not completed. The host should retry the DPACC or APACC access.
The previous transaction might be either a debug port or an access port access. Accesses to the debug port are stalled, by returning WAIT, until any previous access port transaction has completed.
Normally, if software detects a WAIT response, it retries the same transfer. This enables the protocol to process data as quickly as possible. However, if the software has retried a transfer a number of times, permitting enough time for a slow interconnect and memory system to respond, it might write to the ABORT register, to cancel the operation. This signals to the active access port that it can terminate the transfer it is currently attempting and permits access to other parts of the debug system. An access port might not be able to terminate a transfer on its ASIC interface. However, on receiving an ABORT, the access port must free its JTAG interface.
No request is generated at the Update-DR state and the shifted-in data is discarded. The captured value of ReadResult[31:0] is Unpredictable.
You can detect a WAIT response without shifting through the entire DP or AP Access Register, see the response details in Table 9.3.
At the Capture-DR state, if the previous transaction has not completed a WAIT response is generated. When this happens, if the Overrun Detect flag is set, the Sticky Overrun flag, STICKYORUN, is set. See Control/Status Register, CTRL/STAT for more information about the Overrun Detect and Sticky Overrun flags.
While the previous transaction remains not completed, subsequent scans also receive a WAIT response.
When the previous transaction has completed, any more APACC transactions are abandoned and scans respond immediately with an OK/FAULT response. However, debug port registers can be accessed. In particular the CTRL/STAT register can be accessed, to confirm that the Sticky Overrun flag is set and to clear the flag after gathering any required information about the overrun condition. See Overrun detection for more information.
As explained in OK/FAULT response to a DPACC or APACC access, a debug port or access port register access is initiated at the Update-DR state of one DPACC or APACC access, and the result of the access is returned at the Capture-DR state of the following DPACC or APACC access. However, the second access generates a WAIT response if the requested register access has not completed.
The JTAG clock, TCK, is asynchronous to the internal clock of the system being debugged. The time required for an access to complete includes clock cycles in both domains. However, the timing between the Update-DR state and the Capture-DR state only includes TCK cycles. In Figure 9.3, there are two paths from the Update-DR state, where the register access is initiated, to the Capture-DR state, where the response is captured:
a direct path through Select-DR-Scan
a path through Run-Test/Idle and Select-DR-Scan.
If the second path is followed, the state machine can spend any number of TCK cycles spinning in the Run-Test/Idle state. This means it is possible to vary the number of TCK cycles between the Update-DR and Capture-DR states.
A JTAG implementation might impose an implementation-defined lower limit on the number of TCK cycles between the Update-DR and Capture-DR states. It always generates an immediate WAIT response if Capture-DR is entered before this limit has expired. Although any debugger must be able to recover successfully from any WAIT response, ARM recommends that debuggers must be able to adapt to any implementation-defined limit.
In addition, when accessing access port registers, or accessing a connected device through an access port, there might be other variable response delays in the system. A debugger that can adapt to these delays, avoiding wasted WAIT scans, operates more efficiently and provides higher maximum data throughput.
As described in OK/FAULT response to a DPACC or APACC access and Minimum response times, a debug port or access port register access is initiated at the Update-DR state of one DPACC or APACC access and the result of the access is returned at the Capture-DR state of the following DPACC or APACC access. Table 9.4 summarizes the target responses, at the Capture-DR state, for every possible DPACC and APACC access in the previous scan.
The target responses shown in Table 9.4 are independent of the operation being performed in the current DPACC or APACC scan. In the table, Read result is the data shifted out as Data[34:3] and ACK is decoded from the data shifted out as Data[2:0].
|Previous scan, at Update-DR state||Current scan, at Capture-DR state||Notes|
|R/W||IR||ADDR ||Sticky||AP state||Read result||ACK|
|X||X||bXX||X||Busy||UNP||WAIT||Can cause Sticky Overrun flag to be set|
|R||DPACC||b01||X||Not Busy||CTRL/STAT||OK/FAULT||Returns CTRL/STAT value|
|b10||SELECT||Returns SELECT value|
|b00 or b11||No readable DP registers at addresses b00 and b11|
|W||DPACC||b01||X||Not Busy||UNP||OK/FAULT||Write to CTRL/STAT|
|b10||Write to SELECT|
|b00 or b11||Write ignored|
|R||APACC||bXX||No||Ready||See Notes||OK/FAULT||See footnote|
|Error||UNP||Sticky Error flag is set|
|Error||UNP||Sticky Error flag is set|
|X||APACC||bXX||Yes||X||UNP||OK/FAULT||Previous transaction was discarded|
 The Previous scan is the most recent scan for which the ACK response at the Capture-DR state was OK/FAULT. Updates made following a WAIT response are discarded.
 A[3:2] in the DPACC or APACC access.
 The state of the AP when the current scan reaches the Capture-DR state, or the response from the AP at that time.
 UNP = Unpredictable.
 If Pushed Verify or Pushed Compare is enabled, the behavior is Unpredictable. Otherwise, returns the value of the AP Register addressed on the previous scan.
 If Pushed Verify or Pushed Compare is enabled, the previous transaction performed the required pushed operation, which might have set the Sticky Compare flag, see Pushed compare and pushed verify operations. Otherwise, the data captured at the previous scan has been written to the AP register requested.
The ACK column, for the Current scan, at Capture-DR state section of Table 9.4, shows the responses the host might receive after initiating a DPACC or APACC access.
|JTAG access type||ACK from target||Suggested host action in response to ACK|
|Read||OK/FAULT||Capture read data.|
|Write||OK/FAULT||No more action required.|
|Read or Write||WAIT|
Repeat the same access until either an OK/FAULT ACK is received or the wait timeout is reached.
If necessary, use the DAP ABORT register to enable access to the AP.
|Read or Write||Invalid ACK||Assume a target or line error has occurred and treat as a fatal error.|
Access the DP Abort Register, to force a DAP abort.
This is the JTAG-DP implementation of the Abort Register, see Abort Register, ABORT.
- Operating mode
When the ABORT instruction is the current instruction in the IR, the serial path between TDI and TDO is connected to a 35-bit scan chain that is used to access the Abort Register.
The debugger must scan the value
0x0000008into this scan chain. This value:
writes the RnW bit as 0
writes the A[3:2] field as b00
writes 1 into bit 0, the DAPABORT bit, of the Abort Register.
The effect of writing any other value into this scan chain is Unpredictable.
Figure 9.8 shows the bit order of the ABORT scan chain.