The JTAG-DP comprises:
a DAP State Machine (JTAG)
an Instruction Register (IR) and associated IR scan chain, used to control the behavior of the JTAG and the currently-selected data register
a number of Data Registers (DRs) and associated DR scan chains, that interface to the registers in the JTAG-DP.
Figure 9.3 shows the JTAG state machine.
From IEEE Std. 1149.1-2001. Copyright 2001 IEEE. All rights reserved.
When using an ARM Debug Interface, for the debug process to work correctly, systems must not remove power from the JTAG-DP during a debug session.
The TDI signal into the DAP is the start of the scan chain and the TDO signal out of the DAP is the end of the scan chain.
Referring to the DAP State Machine (JTAG) shown in Figure 9.3:
When the JTAG goes through the Capture-IR state, a value is transferred onto the Instruction Register (IR) scan chain. The IR scan chain is connected between TDI and TDO.
While the JTAG is in the Shift-IR state, and for the transition from Capture-IR to Shift-IR, the IR scan chain advances one bit for each tick of TCK. This means that on the first tick, the LSB of the IR is output on TDO, bit  of the IR is transferred to bit , bit  is transferred to bit , for example. The MSB of the IR is replaced with the value on TDI.
When the JTAG goes through the Update-IR state, the value scanned into the scan chain is transferred into the Instruction Register.
When the JTAG goes through the Capture-DR state, a value is transferred from one of a number of Data Registers (DRs) onto one of a number of Data Register scan chains, connected between TDI and TDO.
This data is then shifted while the JTAG is in the Shift-DR state, in the same manner as the IR shift in the Shift-IR state.
When the JTAG goes through the Update-DR state, the value scanned into the scan chain is transferred into the Data Register
When the JTAG is in the Run-Test/Idle state, no special actions occur. Debuggers can use this as a true resting state.
The nTRST signal only resets the JTAG state machine logic. nTRST asynchronously takes the JTAG state machine logic to the Debug-Logic-Reset state. As shown in Figure 9.3, the Debug-Logic-Reset state can also always be entered synchronously from any state by a sequence of five TCK cycles with TMS high. However, depending on the initial state of the JTAG, this might take the state machine through one of the Update states, with the resulting side effects.
In the DAP, the debug port registers are only reset when DBGRESETn is asserted.