This section describes the Serial Wire Debug Port (SW-DP) interface. In particular, it describes the Serial Wire Debug (SWD) protocol and how this protocol provides access to the debug port registers. These registers are described in detail in DAP programmer’s model.
The SW-DP operates with a synchronous serial interface. This uses a single bidirectional data signal and a clock signal.
Each sequence of operations on the wire consists of two or three phases:
- Packet request
The external host debugger issues a request to the debug port. The debug port is the target of the request.
- Acknowledge response
The target sends an acknowledge response to the host.
- Data transfer phase
This phase is only present when either:
a data read or data write request is followed by a valid (OK) acknowledge response
the ORUNDETECT flag is set to 1 in the CTRL/STAT Register, see Control/Status Register, CTRL/STAT.
The data transfer is one of:
target to host, following a read request (RDATA)
host to target, following a write request (WDATA).