The DAP internal interface is a 32-bit data bus. 8-bit or
16-bit transfers can be formed on AHB according to the Size field
in the Control/Status Word Register at
The AddrInc field in the Control/Status Word Register enables optimized
use of the DAP internal bus to reduce the number of accesses from
the tools to the DAP. It indicates if the entire data word is to
be used to pack more than one transfer. Address incrementing is
automatically enabled if packet transfers are initiated so that
multiple transfers are carried out at the sequential addresses.
The size of the address increment is based on the size of the transfer.
Examples of the transactions are:
For an unpacked 16-bit write to an address base of
0x2(CSW[2:0]=b001, CSW[5:4]=b01), HWDATA[31:16] is written from bits [31:16] in the Data Read/Write Register.
For an unpacked 8-bit read to an address base of
0x1, (CSW[2:0]=b000, CSW[5:4]=b01), HRDATA[31:16] and HRDATA[7:0] are zeroed and HRDATA[15:8] contains read data.
For a packed byte write at a base address
0x2, (CSW[2:0]=b000, CSW[5:4]=b10), four write transfers are initiated, the order of data being sent is:
HWDATA[23:16], from DRW[23:16], to HADDR[31:0]=
HWDATA[31:24], from DRW[31:24], to HADDR[31:0]=
HWDATA[7:0], from DRW[7:0], to HADDR[31:0]=
HWDATA[15:8], from DRW[15:8], to HADDR[31:0]=
For a packed halfword reading at a base address of
0x2, (CSW[2:0]=b001, CSW[5:4]=b10), two read transfers are initiated:
HRDATA[31:16] is stored into DRW[31:16] from HADDR[31:0]=
HRDATA[15:0] is stored into DRW[15:0] from HADDR[31:0]=
If the current transfer is aborted or the current transfer receives an ERROR response, the AHB-AP does not complete the following packed transfers.