The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler mode. Processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the exception handler. The following features enable efficient, low latency exception handling:
Automatic state saving and restoring. The processor pushes state registers on the stack when entering the exception and pops them when exiting the exception with no instruction overhead.
For information on what content is stacked, see Pre-emption.
Automatic reading of the vector table entry that contains the exception handler address.
Vector table entries are ARM or Thumb interworking compatible values.
Bit of the vector value is loaded into the EPSR T-bit on exception entry. Creating a table entry with bit  clear generates a Hard Fault on the first instruction of the handler corresponding to this vector.
Closely-coupled interface between the processor and the NVIC to enable efficient processing of interrupts and processing of late-arriving interrupts with higher priority.
Configurable number of interrupts, from 1, 8, 16, or 32.
Two bits of configurable interrupt priority providing four levels.
Separate stacks for Handler and Thread modes if the Operating System (OS) extension is implemented.
Exception control transfer using the calling conventions of the C/C++ standard ARM Architecture Procedure Call Standard (AAPCS). For more information, see the Application Binary Interface for the ARM Architecture (The Base Standard).
Priority masking to support critical regions.
The number of interrupts are configured during implementation. Software can choose to enable a subset of the configured number of hardware interrupts.