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4.9. Activation levels

When no exceptions are active, the processor is in Thread mode. When an exception or fault handler is active, the processor enters Handler mode. Table 4.7 lists the stacks and associated active exception and activation levels.

Stack activation levels
Active exceptionActivation levelStack
NoneThread modeMain or process
Exception activeAsynchronous pre-emption levelMain
Fault handler activeAsynchronous or Synchronous pre-emption levelMain

Table 4.8 lists the transition rules for all exception types and how they relate to the access rules and stack model.

Exception transitions
Active exceptionTriggering eventTransition typeStack
ResetReset signal ThreadMain
ISR or NMI[1]Set-pending software instruction or hardware signalAsynchronous pre-emptionMain
Hard Fault Any faultSynchronous or asynchronous pre-emptionMain
SVC[2] SVC instructionSynchronous pre-emptionMain

[1] Nonmaskable interrupt.

[2] Supervisor Call.

Table 4.9 lists exception subtype transitions.

Exception subtype transitions

Intended activation subtype

Triggering eventActivationPriority effect
ThreadReset signalAsynchronous Immediate, thread is lowest
Interrupt or NMIHardware signal or set-pendAsynchronous Pre-empt according to priority

SVC instruction

SynchronousIf the priority programmed for the SVCall exception is higher than the currently executing priority, the SVCall exception is taken. If not, the SVC escalates to a HardFault.
PendSVSoftware pend requestAsynchronousPre-empt according to priority
SysTickCounter reaches zero or set-pendAsynchronousPre-empt according to priority
HardFaultAny faultSynchronous or asynchronous[1]Higher than all except NMI[2]

[1] Activation depends on the cause of the fault.

[2] If a Hard Fault occurs when the processor is executing an NMI or Hard Fault handler, the processor enters the architectural lock-up state. See Lock-up for more information.

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