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A.1. Clocks and Resets

Table A.1 lists the clock and reset signals.

Reset signals
HCLKInputMain processor clock.
DAPCLKaInputAHB-AP clock. Can be connected to HCLK or can be asynchronous to HCLK if there are other APs in the SoC that cannot operate at full HCLK.
DBGRESETn[1]InputReset for debug logic.
SYSRESETnInputSystem reset. Resets processor and non-debug portion of NVIC. Debug components are not reset by SYSRESETn.
DAPRESETnaInputAHB-AP reset, DAPCLK domain

[1] Only present if the processor is configured with debug.

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