Table A.1 lists the clock and reset signals.
|HCLK||Input||Main processor clock.|
|DAPCLKa||Input||AHB-AP clock. Can be connected to HCLK or can be asynchronous to HCLK if there are other APs in the SoC that cannot operate at full HCLK.|
|DBGRESETn||Input||Reset for debug logic.|
|SYSRESETn||Input||System reset. Resets processor and non-debug portion of NVIC. Debug components are not reset by SYSRESETn.|
|DAPRESETna||Input||AHB-AP reset, DAPCLK domain|
 Only present if the processor is configured with debug.