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A.2. Miscellaneous

Table A.2 lists the miscellaneous signals.

Miscellaneous signals
NameDirectionDescription
LOCKUPOutputIndicates that the core is locked up.
HALTED[1]OutputIndicates halting debug mode. HALTED remains asserted while the core is in debug.
SYSRESETREQOutputRequests that the system reset controller resets the core. It is cleared on reset. Do not connect this line directly to the reset input, use a flop to hold the reset LOW for a cycle.
EDBGRQaInputExternal debug request.
DBGRESTARTaInput

External restart request.

If you are not using this signal to connect to a CTI, tie this input LOW.

Contact ARM for connection information if you are using this signal to connect to a CTI.

DBGRESTARTEDaOutput

Handshake for DBGRESTART.

If you are not using this signal to connect to a CTI, leave unconnected.

Contact ARM for connection information if you are using this signal to connect to a CTI.

[1] Only present if the processor is configured with debug.

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