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A.5. Memory interfaces

Table A.5 lists the signals of the ITCM interface.

ITCM interface
NameDirectionDescription
ITCMENOutputEnable to memory. Either ITCMRD or ITCMWR is also set.
ITCMRDOutputRead Enable to memory, set only if ITCMEN is set.
ITCMWROutputWrite Enable, set if and only if ITCMBYTEWR is non zero, and only if ITCMEN is set.
ITCMBYTEWR[3:0]OutputWrite Enables for each byte, if any of these are set, ITCMWR is also set.
ITCMADDR[19:2]OutputAddress to read from or write to.
ITCMWDATA[31:0]Output

Data to be written to ITCM. Only bytes that ITCMBYTEWR is set for are valid.

ITCMRDATA[31:0]InputData read from the ITCMADDR. All reads are 32 bit.
CFGITCMSZ[3:0]InputSize encoded onto 4 bits. Tie off at synthesis time to optimize logic for speed, or wire to a static value at run time to permit more flexibility.
CFGITCMEN[1:0]Input

ITCM Alias Enables. Sets the value written into the Upper and Lower ITCM Alias Enable bits in the Auxiliary Control Register on reset.

CFGITCMEN[1] sets the Upper Alias Enable bit and CFGITCMEN[0] sets the Lower Alias Enable bit.

The value on these pins must be held constant for at least 2 cycles before SYSRESETn is deasserted.

Table A.6 lists the signals of the DTCM interface.

DTCM interface
NameDirectionDescription
DTCMENOutputEnable to memory. Either DTCMRD or DTCMWR is also set.
DTCMRDOutputRead Enable to memory, set only if DTCMEN is set.
DTCMWROutputWrite Enable, set if and only if DTCMBYTEWR is non zero, and only if DTCMEN is set.
DTCMBYTEWR[3:0]OutputWrite Enables for each byte. If any of these are set, DTCMWR is also set.
DTCMADDR[19:2]OutputAddress to read from or write to.
DTCMWDATA[31:0]OutputData to be written to DTCM. Only bytes that DTCMBYTEWR is set for are valid.
DTCMRDATA[31:0]InputData read from the DTCMADDR. All reads are 32-bit.
CFGDTCMSZ[3:0]InputSize encoded onto 4 bits. Tie off at synthesis time to optimize logic for speed, or wire to a static value at run time to permit more flexibility.

Table A.7 lists the signals of the Debug ITCM interface.

Debug ITCM interface
NameDirectionDescription
DBGITCMENOutputEnable to memory. Either DBGITCMRD or DBGITCMWR is also set.
DBGITCMRDOutputRead Enable to memory, set only if DBGITCMEN is set.
DBGITCMWROutputWrite Enable, set if and only if DBGITCMBYTEWR is non zero, and only if DBGITCMEN is set.
DBGITCMBYTEWR[3:0]OutputWrite Enables for each byte, if any of these are set, DBGITCMWR is also set.
DBGITCMADDR[19:2]OutputAddress to read from or write to.
DBGITCMWDATA[31:0]Output

Data to be written to ITCM. Only bytes that DBGITCMBYTEWR is set for are valid.

DBGITCMRDATA[31:0]InputData read from the DBGITCMADDR. All reads are 32 bit.

Table A.8 lists the signals of the Debug DTCM interface.

Debug DTCM interface
NameDirectionDescription
DBGDTCMENOutputEnable to memory. Either DBGDTCMRD or DBGDTCMWR is also set.
DBGDTCMRDOutputRead Enable to memory, set only if DBGDTCMEN is set.
DBGDTCMWROutputWrite Enable, set if and only if DBGDTCMBYTEWR is non zero, and only if DBGDTCMEN is set.
DBGDTCMBYTEWR[3:0]OutputWrite Enables for each byte. If any of these are set, DBGDTCMWR is also set.
DBGDTCMADDR[19:2]OutputAddress to read from or write to.
DBGDTCMWDATA[31:0]OutputData to be written to DTCM. Only bytes that DBGDTCMBYTEWR is set for are valid.
DBGDTCMRDATA[31:0]InputData read from the DBGDTCMADDR. All reads are 32-bit.
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