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5.1. About clocks and resets

The processor has one functional clock input, HCLK, and one functional reset signal, SYSRESETn.

If debug is implemented there is also an AHP-AP clock, DAPCLK, a debug reset signal, DBGRESETn, and an AHB-AP JTAG reset, DAPRESETn. DAPCLK and DAPRESETn relate to the Debug Access Port (DAP) logic and the debug reset signal DBGRESETn relates to the debug logic clocked by HCLK.

Depending on your system requirements, DAPCLK can be either tied to HCLK or asynchronous to HCLK. You might want DAPCLK to run at a lower frequency than HCLK if, for example, you have other Access Ports in your system that are unable to run at the full HCLK. You can, alternatively, use the DAPCLK clock enable signal, DAPCLKEN, to reduce the effective DAPCLK frequency.

The SYSRESETn signal resets the entire processor system with the exception of debug, and must be used to reset the external AHB bus. The DBGRESETn signal resets all the debug logic in the processor, when present.

The following are not reset:

  • the TCMs, when present

  • the register file.

Figure 5.1 shows the reset signals for the processor.

Figure 5.1. Reset signals

Figure 5.1. Reset signals


Both DBGRESETn and SYSRESETn must be asserted at power on reset.

Depending on your requirements, you might want to reset the system outside the processor independent of the state of SYSRESETREQ. If this is the case, ensure that:

  • Any logic required for debug is not reset.

  • SYSRESETREQ is not connected combinatorially to SYSRESETn. SYSRESETREQ must be registered to ensure that SYSRESETn is driven for the minimum reset time of your FPGA. SYSRESETREQ is cleared by SYSRESETn.

  • DBGRESETn is driven at power on reset and not by SYSRESETREQ otherwise the debugger cannot maintain a connection when the processor is reset.

  • If DBGRESETn is driven SYSRESETn must also be driven.


If you do not reset the system at the same time as the processor, you must also ensure accesses that might be in progress as reset occurs do not disrupt the system.

You must ensure that SYSRESETn and DBGRESETn are:

  • held LOW for a minimum of 3 cycles

  • deasserted synchronously to HCLK.

You can stop all of the processor clocks indefinitely without loss of state.


  • When the External AHB system and the processor are held in reset by SYSRESETn, the debugger can only access the debug portion of the PPB space of the processor and the TCMs. The debugger cannot access external memory space.

  • If SYSRESETn is asserted during a DAP access to the external AHB system or to the PPB space, except to debug registers, the results of the access cannot be guaranteed. For example, a read transaction might receive corrupt data and a faulting transaction might not be recognized by the DAP.

  • You must ensure that DAPRESETn is held LOW for a minimum of two cycles and deasserted synchronously to DAPCLK.

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