This section describes the registers used to program the AHB-AP:
Table 9.2 shows the AHB access port registers.
|R/W||32||Control/Status Word, CSW|
|R/W||32||Transfer Address, TAR|
|R/W||32||-||Data Read/Write, DRW|
|R/W||32||-||Banked Data 0, BD0|
|R/W||32||-||Banked Data 1, BD1|
|R/W||32||-||Banked Data 2, BD2|
|R/W||32||-||Banked Data 3, BD3|
|RO||32||Debug ROM table|
|RO||32||Identification Register, IDR|
The section describes the AHB access port registers:
This is the control word used to configure and control transfers through the AHB interface.
Figure 9.3 shows the Control/Status Word Register bit assignments.
Table 9.3 lists the bit assignments.
Specifies the protection signal encoding to be output on HPROT[3:0].
Reset value is noncacheable, non-bufferable, data access, privileged = b0011.
|||RO||SPIStatus||Indicates the status of the SPIDEN port. Always reads as b1.|
Specifies the mode of operation:
b0000 = Normal download/upload model
b0001-b1111 = Reserved SBZ.
Reset value = b0000.
|||RO||TrInProg||Transfer in progress. This field indicates if a transfer is currently in progress on the AHB master port.|
Indicates the status of the DBGEN port. Always reads as b1 = AHB transfers permitted.
Auto address increment and packing mode on Read or Write data access. Only increments if the current transaction completes without an Error Response. Does not increment if the transaction completes with an Error Response or the transaction is aborted.
address incrementing and packed transfers are not performed on access
to Banked Data registers
and wraps within a 1KB address boundary, for example, for word incrementing
b00 = auto increment off
b01 = increment, single.
Single transfer from corresponding byte lane.
b10 = increment, packed
Word = same effect as single increment.
Byte/Halfword. Packs four 8-bit transfers or two 16-bit transfers into a 32-bit DAP transfer. Multiple transactions are carried out on the AHB interface.
b11 = Reserved SBZ, no transfer.
Size of address increment is defined by the Size field, bits [2:0].
Reset value = b00.
|||-||-||Reserved SBZ, R/W = b0|
Size of the data access to perform:
b000 = 8 bits
b001 = 16 bits
b010 = 32 bits
b011-b111 = Reserved SBZ.
Reset value = b010.
Table 9.4 shows the AHB-AP Transfer Address Register bit assignments.
Table 9.5 shows the AHB-AP Data Read/Write Register bit assignments.
BD0-BD3 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the Transfer Address Register (TAR) within a four-location boundary. BD0 reads/writes from TA. BD1 reads/writes from TA+4. Table 9.6 shows the AHB-AP Banked Data Register bit assignments.
If DAPADDR[7:4] =
Auto address incrementing is not performed on DAP accesses to BD0-BD3.
Banked transfers are only supported for word transfers. Non-word banked transfers are reserved and Unpredictable. Transfer size is currently ignored for banked transfers.
Table 9.7 shows the ROM Address Register bit assignments.
The register reset value is
Figure 9.4 shows the AHB-AP Identification Register bit assignments.
Table 9.8 shows the AHB-AP Identification Register bit assignments.
|[31:28]||RO||Revision. Reset value is |
Reset value is |
|[23:17]||RO||JEDEC code. Reset value is |
|||RO||ARM AP. Reset value is b1.|
|[7:0]||RO||Identity value. Reset value is |
 Using JEDEC bank