The processor watchpoints are described as semiprecise. When the processor triggers a watchpoint, it executes one more instruction after the one that triggered the watchpoint, before entering debug state. The number of extra instructions is constant, independent of bus or instruction cycle times. If another debug event causes the processor to enter debug state earlier, for example as a result of a breakpoint, the processor enters debug state with more than one flag set in the DFSR. See Debug Fault Status Register for more information.
The instruction executed can include an exception return sequence or any number of exception entry sequences.