The processor has two memory interfaces:
See Memory interfaces for descriptions of the ITCM and DTCM interface signals.
The processor does not support wait states for the memory interfaces.
This section describes the ITCM interface. This description also applies to the DTCM interface.
Table 10.2 shows the ITCMBYTEWR value for different sizes of write accesses.
|ITCMBYTEWR value||Size of write|
|4'b0011 or 4'b1100||Halfword|
|4'b0001, 4'b0010, 4'b0100 or 4'b1000||Byte|
Figure 10.1 shows the write signal timings for the ITCM interface.
For writes, the write address, write data, and control signals are driven on the same cycle. The write enable signals ensure individual bytes within a word are written without corrupting the other bytes in the same word. For example, if ITCMBYTEWR is asserted, bits ITCMBYTEWR[15:8] are written in to byte 1 of the word at address ITCMADRR.
Figure 10.1 shows the read signal timings for the ITCM interface.
Table 10.3 shows the TCM sizes that are defined through input pins. These sizes are factored into both the core and debug address decoders.
If you use other values than those that Table 10.3 shows, the effects are Unpredictable.