You copied the Doc URL to your clipboard.

10.5. Memory interfaces

The processor has two memory interfaces:

  • ITCM

  • DTCM.

See Memory interfaces for descriptions of the ITCM and DTCM interface signals.

The processor does not support wait states for the memory interfaces.

Note

This section describes the ITCM interface. This description also applies to the DTCM interface.

Table 10.2 shows the ITCMBYTEWR value for different sizes of write accesses.

Byte-write size
ITCMBYTEWR valueSize of write
4'b1111Word
4'b0011 or 4'b1100Halfword
4'b0001, 4'b0010, 4'b0100 or 4'b1000Byte

Figure 10.1 shows the write signal timings for the ITCM interface.

Figure 10.1. ITCM write signal timings

Figure 10.1. ITCM write signal timings

For writes, the write address, write data, and control signals are driven on the same cycle. The write enable signals ensure individual bytes within a word are written without corrupting the other bytes in the same word. For example, if ITCMBYTEWR[1] is asserted, bits ITCMBYTEWR[15:8] are written in to byte 1 of the word at address ITCMADRR.

Figure 10.1 shows the read signal timings for the ITCM interface.

Figure 10.2. ITCM read signal timings

Figure 10.2. ITCM read signal timings

Table 10.3 shows the TCM sizes that are defined through input pins. These sizes are factored into both the core and debug address decoders.

Instruction and Data TCM sizes

CFGITCMSZE or

CFGDTCMSZE

TCM size
4'h00KB
4'h11KB
4'h22KB
4'h34KB
4'h48KB
4'h516KB
4'h632KB
4'h764KB
4'h8128KB
4'h9256KB
4'hA512KB
4'hB1MB

If you use other values than those that Table 10.3 shows, the effects are Unpredictable.

Was this page helpful? Yes No