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2.1.2. MBISTINDATA and MBISTOUTDATA mapping

This section describes how the different RAM arrays are mapped on MBISTINDATA and MBISTOUTDATA:

Instruction data and Data data RAMs

The Instruction data RAMs are selected using bits MBISTARRAY[7:4]. The Data data RAMs are selected using bits MBISTARRAY[16:13]. This cache is byte-writable. All write enable bits must be controllable separately.

Both caches consist of eight RAM arrays for storing the associated data. See Table 2.3 for more information. For both data caches two arrays are tested in parallel and the same data is sent to each CPU. For n=0 to n=3 Data in and Data out buses are mapped as Figure 2.1 and Figure 2.2 show.

Figure 2.1. MBISTINDATA[63:0] format for Instruction data RAM and Data data RAM

Figure 2.1. MBISTINDATA[63:0] format for Instruction
data RAM and Data data RAM

The width of MBISTINDATA in a configuration with parity is MBISTINDATA[71:0].

Figure 2.2. MBISTOUTDATA[255:0] format data out for Instruction data RAM and Data data RAM

Figure 2.2. MBISTOUTDATA[255:0]
format data out for Instruction data RAM and Data data RAM

In a configuration with parity the width of MBISTOUTDATA is MBISTOUTDATA[287:0]

Instruction data RAMs have a word write enable, controlled by MBISTWRITEEN when in BIST mode. Data data RAMs have a byte write enable, controlled by MBISTBE[3:0] as Table 2.4 shows.

Table 2.4. Data data RAM byte write enable control
MBISTBE bitDescription
0Byte 0, bits [7:0]
1Byte 1, bits [15:8]
2Byte 2, bits [23:16]
3Byte 3, bits [31:24]

Instruction tag, Data tag, and SCU tag RAMs

Instruction tag RAMs, Data tag RAMs and SCU tag RAMs all consist of four arrays per CPU. Data tag RAMs and SCU tag RAMs are identical in structure. Two arrays are tested in parallel for each CPU.

Table 2.5 shows the MBISTARRAY bits used to select each tag RAM.

Table 2.5. MBISTARRAY bit usage for tag RAMs
MBISTARRAY bitsDescription
[3:2]Select the Instruction tag array
[12:11]Select the Data tag array
[19:18]Select the SCU tag array

Figure 2.3 shows the data mapping on MBISTINDATA for Instruction tag RAM.

Figure 2.3. MBISTINDATA[63:0] format for Instruction tag RAM

Figure 2.3. MBISTINDATA[63:0] format for Instruction
tag RAM

Figure 2.4 shows the data mapping on MBISTOUTDATA for Instruction tag RAM.

Figure 2.4. MBISTOUTDATA[255:0] format for Instruction tag RAM

Figure 2.4. MBISTOUTDATA[255:0] format for Instruction
tag RAM

Figure 2.5 and Figure 2.6 show the data mapping on MBISTINDATA and MBISTOUTDATA buses for Data tag RAM.

Figure 2.5. MBISTINDATA[63:0] format for Data tag RAM

Figure 2.5. MBISTINDATA[63:0] format for Data
tag RAM

Figure 2.6. MBISTOUTDATA[255:0] format for Data tag RAM

Figure 2.6. MBISTOUTDATA[255:0] format for Data
tag RAM

Figure 2.7 shows the data mapping on MBISTINDATA[63:0] for SCU tag RAM.

Figure 2.7. MBISTINDATA[63:0] for SCU tag RAM

Figure 2.7. MBISTINDATA[63:0] for SCU tag RAM

Figure 2.8 shows the data mapping on MBISTOUTDATA[255:0] for SCU tag RAM.

Figure 2.8. MBISTOUTDATA[255:0] for SCU tag RAM

Figure 2.8. MBISTOUTDATA[255:0] for SCU tag RAM

Figure 2.9 shows the data mapping on MBISTINDATA[63:0] for GHB tag RAM.

Figure 2.9. MBISTINDATA[63:0] for GHB tag RAM

Figure 2.9. MBISTINDATA[63:0] for GHB tag RAM

Figure 2.10 shows the data mapping on MBISTOUTDATA[255:0] for GHB tag RAM.

Figure 2.10. MBISTOUTDATA[255:0] for GHB tag RAM

Figure 2.10. MBISTOUTDATA[255:0] for GHB tag RAM

Table 2.6 shows the MBISTBE bits used to control the tag RAMs.

Table 2.6. Tag RAM control
RAM typeWrite enableMBISTBE bits
SCU tag RAMBit-write enable[22:0]
Data tag RAMBit-write enable[25:0]

Outer RAM

Outer RAM consists of one array per CPU. It is a bit-writable RAM. Bit-write enables must be controllable separately.

MBISTARRAY[17] selects the Outer RAM array.

Figure 2.11 shows the data mapping on MBISTINDATA for Outer RAM.

Figure 2.11. MBISTINDATA[63:0] format for Outer RAM

Figure 2.11. MBISTINDATA[63:0] format for Outer
RAM

Figure 2.12 shows the data mapping on MBISTOUTDATA[255:0] for Outer RAM.

Figure 2.12. MBISTOUTDATA[255:0] format for Outer RAM

Figure 2.12. MBISTOUTDATA[255:0] format for Outer
RAM

Branch Target Address Cache RAM

Branch Target Address Cache (BTAC) RAMs consist of two arrays, one for control and one for target. The target array is always 32 bits wide.

MBISTARRAY[1:0] selects the BTAC arrays. They are word-writable, controlled by MBISTWRITEEN when in BIST mode.

Figure 2.13 shows the data mapping for BTAC RAM.

Figure 2.13. MBISTINDATA[63:0] format for BTAC RAM

Figure 2.13. MBISTINDATA[63:0] format for BTAC
RAM

Figure 2.14 shows the data mapping on MBISTOUTDATA[255:0] for BTAC RAM.

Figure 2.14. MBISTOUTDATA[255:0] format for BTAC RAM

Figure 2.14. MBISTOUTDATA[255:0] format for BTAC
RAM

TLB RAM

TLB RAM consists of two arrays. MBISTARRAY[10:9] selects these arrays. The TLB arrays are word-writable, controlled by MBISTWRITEEN when in BIST mode.

Figure 2.15 shows the data mapping on MBISTINDATA[63:0] for TLB RAM.

Figure 2.15. MBISTINDATA[63:0] format for TLB RAM

Figure 2.15. MBISTINDATA[63:0] format for TLB
RAM

Figure 2.16 shows the MBISTOUTDATA data mapping for TLB RAM.

Figure 2.16. MBISTOUTDATA[255:0] format for data out for TLB RAM

Figure 2.16. MBISTOUTDATA[255:0] format for data
out for TLB RAM

Global History Buffer RAMs

Global History Buffer (GHB) RAM consists of four arrays which are four bits wide. Address space is 512 words. MBISTARRAY[8] selects the GHB arrays.

The GHB arrays are bit-writable, controlled by MBISTBE[11:0] when in BIST mode.

Figure 2.17 shows the data mapping on the MBISTINDATA bus for GHB tag RAM.

Figure 2.17. MBISTINDATA[63:0] format for GHB tag RAM

Figure 2.17. MBISTINDATA[63:0] format for GHB
tag RAM

Figure 2.18. MBISTOUTDATA[255:0] format for GHB tag RAM

Figure 2.18. MBISTOUTDATA[255:0] format for GHB tag RAM

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