The MBIST controller is supplied with industry-standard pattern algorithms and a bit-line stress algorithm. You can group algorithms together to create a specific memory test methodology for your product.
Table 3.1 describes the supported algorithms, and Pattern specification describes their use. The N values in the table indicate the number of RAM accesses per address location and give an indication of the test time when using that algorithm.
|b000000||Write Solids||1N||Write a solid pattern to memory|
|b000001||Read Solids||1N||Read a solid pattern from memory|
|b000010||Write Checkerboard||1N||Write a checkerboard pattern to memory|
|b000011||Read Checkerboard||1N||Read a checkerboard pattern from memory|
|b000100||March C+ (x-fast)||14N||March C+ algorithm, incrementing X-address first|
|b001011||March C+ (y-fast)||14N||March C+ algorithm, incrementing Y-address first|
|b000101||Fail Pattern||6N||Tests memory failure detection capability|
|b000110||Read Write March (x-fast)||6N||Read write march pattern, incrementing X-address first|
|b000111||Read Write March (y-fast)||6N||Read write march pattern incrementing Y-address first|
|b001000||Read Write Read March (x-fast)||8N||Read write read march pattern, incrementing X-address first|
|b001001||Read Write Read March (y-fast)||8N||Read write read march pattern, incrementing y-address first|
|b001010||Bang||18N||Bit-line stress pattern|
|b111111||Go/No-Go||30N||See Table 3.2|
This section describes the MBIST test patterns. An x-fast pattern increments or decrements the X-address counter first. A y-fast pattern increments or decrements the Y-address counter first. MaxXAddr and MaxYAddr fields, MBIR[35:32] and MBIR[31:28] describes the X-address and Y-address counters.
The first four patterns are useful for data retention or IDDQ testing.
- Write Solids
This initializes the RAM with the supplied data seed.
- Read Solids
This reads each RAM location once expecting the supplied data seed.
- Write Checkerboard
This initializes the RAM with a physical checkerboard pattern created by alternating the supplied data seed and its inverse.
- Read Checkerboard
This reads back the physical checkerboard pattern created by alternating the supplied data seed and its inverse.
For the next set of patterns, the following notation describes the algorithm:
represents the data seed.
represents the inverse data seed.
represents a read operation.
represents a write operation.
Increment address starting with 0 until address = addrmax.
Decrement address starting with addrmax until address = 0.
- March C+ (x-fast or y-fast)
This is the industry-standard March C+ algorithm:
(w0) (r0, w1, r1) (r1, w0, r0) decr (r0, w1, r1) decr (r1, w0, r0) (r0)
- Read Write March (x-fast or y-fast)
(w0) (r0, w1) decr (r1, w0) (r0)
- Read Write Read March (x-fast or y-fast)
(w0) (r0, w1, r1) decr (r1, w0, r0) (r0)
This test is always performed in x-fast. It executes multiple consecutive writes and reads effectively stressing a bit-line pair. While this pattern does detect stuck-at faults, its primary intent is to address the analog characteristics of the memory. In the following algorithm description, row 0 indicates a read or write of the data seed to the sacrificial row, this is always the first row of the column being addressed.
(w0) (r0, w0, w0(row 0) × 6) (r0 × 5, w0(row 0), r0) (r0)
If you do not want to implement your own memory test strategy, use the Go/No-Go test pattern that performs the algorithms that Table 3.2 shows.
Table 3.2. Go/No-Go test pattern Sequence Algorithm Data 1 Write Checkerboard Data seed 2 Read Checkerboard Data seed 3 Write Checkerboard Data seed 4 Read Checkerboard Data seed 5 Read Write Read March (y-fast)
This test suite provides a comprehensive test of the arrays. The series of tests in Go/No-Go are the result of the experience in memory testing by ARM memory test engineers.