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2.2.1. Timing

A 58-bit instruction, loaded serially at the start of each test, controls the operation of the MBIST controller. Chapter 3 MBIST Instruction Register describes how to write the instruction.

The timing diagrams in this section show the clock running at two different speeds:

  • the slower clock relates to the clock driven by your ATE

  • the faster clock relates to the clock driven by an on-chip Phase Locked Loop (PLL).

If you do not have an on-chip PLL, both clocks relate to the clock driven by your ATE.

See the Cortex-A9 Technical Reference Manual and Cortex-A9 MPCore Technical Reference Manual for timing information about the processors.

Timing diagrams in the following sections show the procedures for operating the MBIST controller:


The MBIST controller must be reset between each array tested.

Instruction load

To load an MBIST instruction, drive MBISTSHIFT HIGH. At the next rising clock edge, the 58-bit shift sequence begins as Figure 2.20 shows. To enable data input from the ATE, the PLL is in bypass mode, and the clock is not running at test frequency.

Figure 2.20. Loading the MBIST controller instruction

Figure 2.20. Loading the MBIST controller instruction

Starting MBIST

After loading the MBIST instruction, drive MBISTSHIFT LOW and disable CLK. With CLK disabled, drive MBISTRUN HIGH and, after an MBISTRUN setup time, start the PLL at the test frequency as Figure 2.21 shows.

Figure 2.21. Starting the MBIST test

Figure 2.21. Starting the MBIST test

Failure detection

The MBISTRESULT[1] flag goes HIGH two CLK cycles after the controller detects a failure, as Figure 2.22 shows. It stays HIGH if sticky fail is enabled. If stop-on-fail is enabled, the MBISTRESULT[0] flag goes HIGH two cycles later.

Figure 2.22. Detecting an MBIST failure

Figure 2.22. Detecting an MBIST failure


To ensure that the ATE can observe a failure at test speed, specify a sticky fail in the MBIST instruction. See Control field, MBIR[51:46].

Data log retrieval

During a test, the MBIST controller automatically logs the first detected failure. If required, you can retrieve the data log at the end of the test to generate failure statistics. Figure 2.23 and Figure 2.24 show the method of retrieving a data log.


MBISTRESULT[2] is the serial data output for instructions and the data log for CPU0.

MBISTRESULT[3] is the serial data output for instructions and the data log for CPU1.

MBISTRESULT[4] is the serial data output for instructions and the data log for CPU2.

MBISTRESULT[5] is the serial data output for instructions and the data log for CPU3.

After the MBISTRESULT[0] flag goes HIGH, stop the test by putting the PLL in bypass mode and driving MBISTRUN LOW as Figure 2.23 shows. To begin shifting out the data log on MBISTRESULT[5:2], drive MBISTDSHIFT HIGH. The MBISTRESULT[1] error flag goes LOW two cycles after MBISTRUN goes LOW. Data begins shifting out on MBISTRESULT[5:2] two cycles after MBISTDSHIFT goes HIGH.

Figure 2.23. Start of data log retrieval

Figure 2.23. Start of data log retrieval

In Bitmap mode, MBISTRUN can stay high. Asserting MBISTDSHIFT clears MBISTRESULT[1], fail flag, and stalls the controller during datalog retrieval.

When the last data log bit shifts out, drive MBISTDSHIFT LOW as Figure 2.24 shows.

Figure 2.24. End of data log retrieval

Figure 2.24. End of data log retrieval

Table 2.10 shows the format of the data log.

Table 2.10. Data log format
[78:68]Address of the failing location.
[67:4]Failing data bits. These bits are set for faulty bits and cleared for passing bits.
[3:0]The data seed used in the test. See DataWord field, MBIR[27:24].

The address contained in the data log refers to the full address of the failing location as it appears on the MBISTADDR[10:0] port of the MBIST interface of the Cortex-A9 processor.

See also Chapter 4 MBIST Datalog Register.