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1.1. About the MBIST controller

MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory according to a test algorithm. Many industry-standard test algorithms exist.

An MBIST controller generates the correct sequence of reads and writes to all locations of the RAM to ensure that the cells are operating correctly. In doing this, some additional test coverage is achieved in the address and data paths that the MBIST uses. You must only use this MBIST controller with the Cortex-A9 processor to perform memory testing of the Cortex-A9 RAMs.

MBIST mode takes priority over all other modes, for example SCAN, in that the Cortex-A9 RAMs are only accessible to the MBIST controller when MBIST mode is activated.

The MBIST controller controls the MBIST testing of the Cortex-A9 RAMs through the MBIST port of the Cortex-A9 processor. Figure 1.1 shows the Cortex-A9 processor MBIST configuration.

Figure 1.1. Cortex-A9 MBIST configuration

Figure 1.1. Cortex-A9 MBIST configuration

The reset signals of the Cortex-A9 processor must be HIGH in MBIST test mode. Because the MBIST test mode uses some functional paths to access RAMs, the registers on those paths must be out of reset.

See the Cortex-A9 Technical Reference Manual for a description of uniprocessor reset sequences.

See the Cortex-A9 MPCore Technical Reference Manual for a description of multiprocessor reset sequences.

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