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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Differences between issue A and issue B
ChangeLocation
No technical changes-

Table B.2. Differences between issue B and issue C
ChangeLocation
Updated description about the MBIST controllerAbout the MBIST controller
Updated MBIST controller signalsFigure 1.2
Updated MBIST controller interface signalsFigure 1.4
Updated signal names and settings Table 2.2
Updated bit information for the MBIST controller interfacesTable 2.3
Clarified data in for Instruction tag RAMFigure 2.3
Clarified data out for Instruction tag RAMFigure 2.4
Clarified Tag RAM controlTable 2.9
Updated TLB RAM descriptionTLB RAM
Updated Branch Target Address Cache RAM descriptionBranch Target Address Cache RAM

Table B.3. Differences between issue C and issue D
ChangeLocation
MBIST Controller diagram with parity addedFigure 1-3
MBIST signals with parity configuration addedTable 1-2
Information about MBISTINDATA and MBISTOUTDATA sizes in configurations with parity added.MBISTINDATA and MBISTOUTDATA mapping
Arrows removed from pattern descriptionsPattern specification
Datalog failing data out size now 72 bits

Figure 4-1

Field descriptions

MBIST datalog Register formats for configurations with parity and without parity added.About the MBIST Datalog Register
Field descriptions for configurations with parity and without parity added.Field descriptions
MBIST Controller interface signals with parity addedTable A-2

Table B.4. Differences between issue D and issue E
ChangeLocation
No technical changes-

Table B.5. Differences between issue D and issue F
ChangeLocation
Cortex-A9 Multiprocessor TRM added to further readingARM publications
References to reset sequences in TRMs includedAbout the MBIST controller
Lists of pins to tie LOW added MBIST controller interface
Bit field descriptions and titles harmonizedMBISTINDATA and MBISTOUTDATA mapping
Corrections to graphics and textInstruction data and Data data RAMs
Instruction tag, Data tag, and SCU tag RAMs
Outer RAM
Branch Target Address Cache RAM
TLB RAM
Global History Buffer RAMs
Cross-reference about processor timing addedTiming
Corrections to graphicsFigure 2.20
 Figure 2.26
Bit field and title harmonizedCPU On field, MBIR[40:37]
MBIR values correctedTable 3.6

Table B.6. Differences between issue F and issue G
ChangeLocationAffects
Added note about resetting MBIST between arrays tested.TimingAll revisions
Updated Instruction load figureFigure 2.20All revisions
Updated timing diagram for data log retrievalFigure 2.23All revisions
Updated Data log retrieval descriptionData log retrievalAll revisions
Updated timing diagrams for bitmap modeFigure 2.25All revisions
Figure 2.26
Updated field descriptions for MBIST Datalog registerFigure 4.1All revisions
Field descriptions
Updated MBISTOUTDATA signal description in a parity configurationTable A.2All revisions
Update algorithm for Bang pattern description???All revisions

Table B.7. Differences between issue G and issue H
ChangeLocationAffects
Update MBISTBE bus widthMBIST controller interfacer3p2
MBIST controller interface r3p2
MBIST controller interface signalsr3p2
Update nMBISTRESET signal informationMBIST controller interfacer3p2
Update RVALIDM1 signal information MBIST controller interface r3p2
Update Cache RAM signal information MBIST controller interface r3p2
MBISTINDATA and MBISTOUTDATA mappingr3p2
Update signal names MBIST controller interface All revisions
Update MBIST controller reset informationMBIST controller block top level I/Or3p2
Update MBIST data bandwidthTimingr3p2
Update MBIST instruction bandwidthAbout the MBIST instruction registerr3p2
Update MBIR register description for Normal/wide mode Field descriptionsr3p2
Normal mode/wide mode MBIR [0]r3p2

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