The MBIST controller block shown in Figure 2.19 contains two major blocks:
This section describes:
The MBIST controller and the dispatch unit communicate using the following signals:
This signal is an output of the MBIST controller that goes to the dispatch unit. Table 2.10 shows the signals.
Table 2.10. MBISTTX signals MBISTTX bit Description 0 Reset address 1 Increment address 2 Access sacrificial row, used during bang patterns 3 Invert data/instruction data in 4 Checkerboard data 5 Write data 6 Read data 7 Yfast/nXfast 8 Direction 9 Enable bitmap mode 10 Increment go/no go dataword selection 11 Latency stall control
When the instruction shift is enabled, data shifts between the two parts of the BIST engine are on bit 3. In run test mode, this bit is used as invert data information. The MBISTTX[11:0] interface is ARM-specific and intended for use only with the MBIST controller.
This signal is an output of the dispatch unit that goes to the MBIST controller. The behavior of MBISTRX[5:0] is ARM-specific and is intended for use only with the MBIST controller. The address expire signal is set when both the row and column address counters expire. Table 2.11 shows the signals.
Table 2.11. MBISTRX signals MBISTRX bit Description 0 Real-time error flag 1 Shadow pipeline empty 2 CPU0 address/instruction data out/fail data out 3 CPU1 address/instruction data out/fail data out 4 CPU2 address/instruction data out/fail data out 5 CPU3 address/instruction data out/fail data out
|Signal||Direction||Function||Value, MBIST mode||Value, function mode|
|MBISTDATAIN||Input||Serial data in||Toggle||0|
|MBISTDSHIFT||Input||Data log shift||Toggle||0|
|MBISTRESULT[5:0]||Output||Output status bus||Strobe||-|
|MBISTRUN||Input||Run MBIST test||Toggle||0|
|MBISTENABLE||Input||MBIST path enable||Toggle||0|
[a] nRESET and MBISTENABLE must be LOW in functional mode.
ARM recommends a separate reset for the MBIST controller, so that you can soft reset it between tests.
The following signals have additional information:
Preservation of array state is required when performing multiload Automatic Test Pattern Generator (ATPG) runs or when performing IDDQ testing. After performing MBIST tests to initialize the arrays to a required background, the ATPG test procedures must assert SE during all test setup cycles in addition to load/unload. Any clocking during IDDQ capture cycles must have array chip select signals constrained.
During tests, the MBISTRESULT signal indicates failures. You can operate using two modes, by configuring bit  of the engine control section of the instruction register. If bit  is set, the MBISTRESULT signal is asserted for a single cycle for each failed compare. If bit  is not set, the MBISTRESULT signal is sticky, and is asserted from the first failure until the end of the test.
At the completion of the test, the MBISTRESULT signal goes HIGH. The MBISTRESULT[5:2] signal indicates that an address expire for the processor under test has occurred and enables you to measure sequential progress through the test algorithms.