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2.1.1.  MBIST controller interface

The MBIST controller has one MBIST port. See Appendix A Signal Descriptions. Only one set of RAMs is accessed by the MBIST controller at any time.

For a Cortex-A9 MPCore implementation the following pins that must be tied LOW in MBIST mode:

  • DBGEN

  • NIDEN

  • SPIDEN

  • SPNIDEN

  • EDBGRQ

  • DBGRESTART

  • PSELDBG

  • CPUCLKOFF

  • PERIPHCLKEN

  • ACLKENS

  • INCLKENM0

  • INCLKENM1

  • OUTCLKENM0.

  • OUTCLKENM1.

MAXCLKLATENCY must be driven to some value. In other words, it cannot be undriven.

For a Cortex-A9 uniprocessor implementation the following pins that must be tied LOW in MBIST mode:

  • DBGEN

  • NIDEN

  • SPIDEN

  • SPNIDEN

  • EDBGRQ

  • DBGRESTART

  • PSELDBG

  • ACLKENM0

  • ACLKENM1

  • AWREADYM0

  • WREADYM0

  • BVALIDM0

  • RVALIDM0.

  • RVALIDM1.

MAXCLKLATENCY must be driven to some value. In other words, it cannot be undriven.

Table 2.1 shows the MBIST interface signals

Table 2.1. MBIST interface signals
NameTypeDescription
nRESETInputGlobal active LOW reset signal.
CLKInputActive HIGH clock signal. This clock drives the Cortex-A9 processor logic.
MBISTOUTDATA[255:0]Output

Data out bus from all cache RAM blocks.

MBISTENABLEInput

Select signal for cache RAM array. This signal is the select input to the multiplexors that access the cache RAM arrays for test. When asserted, MBISTENABLE takes priority over all other select inputs to the multiplexors.

MBISTARRAY[19:0]Input

One-hot chip enables to select the RAM arrays for test.

MBISTBE[63:0]Input

Global write enable signal for all RAM arrays.

MBISTWRITEENInputGlobal write enable.
MBISTADDR[10:0]Input

Address signal for cache RAM array.

MBISTINDATA[63:0]Input

Data bus to the RAM arrays. Not all RAM arrays use the full data width.

MBISTRUNInputLaunches memory testing.
MBISTDSHIFTInputShift enable for the selected Dispatch Unit Data Log Register.
MBISTSHIFTInputProvides serial load of the MBIST Instruction Register (MBIR).

You can use the MBIST controller for testing the Cortex-A9 processor compiled RAMs. You can also choose to design your own MBIST controller.

For the MBIST to run correctly on the Cortex-A9 processor if the dormant/power off wrappers are implemented, you must set the signals on the Cortex-A9 processor interface as Table 2.2 shows.

Test RAMs for symmetric CPU configurations in parallel, For example, you can test all tag RAMs in symmetric designs in parallel. Send the same data to each CPU using BISTINDATA and the result is read out in parallel on BISTOUTDATA.

For non-uniform configurations you must test the RAMs for each CPU separately.

Table 2.2. Cortex-A9 signal settings for MBIST
Signal nameSetting
CPURAMCLAMP[3:0]b0000
CPUCLAMP[3:0]b0000
SCURAMCLAMPb0

Table 2.3 shows the interfaces between the MBIST controller and the RAMs that MBIST tests in a configuration without parity.

Table 2.3. RAM arrays without parity and MBIST controller interfaces
RAM NameMBISTARRAY bitMBISTINDATA bits[a]MBISTBE bitsMBISTOUTDATA data out chunk bits[b]Max address bits
SCU tag RAM way 3[19][54:32][22:0][54:32][8:0]
SCU tag RAM way 2[19][22:0][22:0][22:0][8:0]
SCU tag RAM way 1[18][54:32][22:0][54:32][8:0]
SCU tag RAM way 0[18][22:0] [22:0][22:0][8:0]
Douter RAM[17][11:0] [11:0][11:0][8:0]
Data data RAM way 3 (arrays 3,7)[16][63:0][7:0][63:0][10:0]
Data data RAM way 2 (arrays 2,6)[15][63:0][7:0][63:0][10:0]
Data data RAM way 1 (arrays 1,5)[14][63:0][7:0][63:0][10:0]
Data data RAM way 0 (arrays 0,4)[13][63:0][7:0][63:0][10:0]
Data tag RAM array 3[12][25:0][25:0][57:32][8:0]
Data tag RAM array 2[12][25:0][25:0][25:0][8:0]
Data tag RAM array 1[11][25:0][25:0][57:32][8:0]
Data tag RAM array 0[11][25:0] [25:0][25:0][8:0]
TLB RAM array 1[10][60:0] -[60:0][7:0]
TLB RAM array 0[9][60:0] -[60:0][7:0]

Global History Buffer arrays 0,1,2,3 normal mode

[8][15:0][15:0][15:0][8:0]

Global History Buffer arrays 0,1,2,3 wide mode

[8][63:0][63:0][63:0][8:0]
Instruction data RAM array 7 (way 3 high)[7][63:32]-[63:32][10:0]
Instruction data RAM array 6 (way 3 low)[7][31:0]-[31:0][10:0]
Instruction data RAM array 5 (way 2 high)[6][63:32]-[63:32][10:0]
Instruction data RAM array 4 (way 2 low)[6][31:0]-[31:0][10:0]
Instruction data RAM array 3 (way 1 high)[5][63:32]-[63:32][10:0]
Instruction data RAM array 2 (way 1 low)[5][31:0]-[31:0][10:0]
Instruction data RAM array 1 (way 0 high)[4][63:32]-[63:32][10:0]
Instruction data RAM array 0 (way 0 low)[4][31:0]-[31:0][10:0]
Instruction tag RAM array 3[3][21:0]-[53:32][8:0]
Instruction tag RAM array 2[3][21:0]-[21:0][8:0]
Instruction tag RAM array 1[2][21:0]-[53:32][8:0]
Instruction tag RAM array 0[2][21:0]-[21:0][8:0]

BTAC RAM target array 1

[1][63:32]-[63:32][10:0]

BTAC RAM control array 1

[1][27:0]-[27:0][10:0]

BTAC RAM target array 0

[0][63:32]-[63:32][10:0]

BTAC RAM control array 0

[0][27:0] -[27:0][10:0]

[a] MBISTINDATA[63:0] is sent to all processors

[b] MBISTOUTDATA[255:0] is sent to each processor data output in parallel This column describes the mapping for the data out chunk [63:0]. You must map the chunks to MBISTOUTDATA[255:0] as described in Table 2.4


Table 2.4. MBISTOUTDATA Bit Assignments, no parity
BitsFunction
[255:192]Data Out for CPU3
[191:128]Data Out for CPU2
[127:64]Data Out for CPU1
[63:0]Data Out for CPU0

Table 2.5 shows the interfaces between the MBIST controller and the RAMs that MBIST tests in a configuration with parity.

Table 2.5. RAM arrays with parity and MBIST controller interfaces
RAM NameMBISTARRAY bitMBISTINDATA bits[a]MBISTBE bitsMBISTOUTDATA data out chunk bits[b]Max address bits
SCU tag RAM way 3[19][62:36][26:0][62:36][8:0]
SCU tag RAM way 2[19][26:0][26:0][26:0][8:0]
SCU tag RAM way 1[18][62:36][26:0][62:36][8:0]
SCU tag RAM way 0[18][26:0][26:0][26:0][8:0]
Douter RAM[17][15:0][15:0][15:0][8:0]
Data data RAM way 3 (arrays 3,7)[16][71:0][7:0][71:0][10:0]
Data data RAM way 2 (arrays 2,6)[15][71:0][7:0][71:0][10:0]
Data data RAM way 1 (arrays 1,5)[14][71:0][7:0][71:0][10:0]
Data data RAM way 0 (arrays 0,4)[13][71:0][7:0][71:0][10:0]
Data tag RAM array 3[12][32:0][32:0][68:36][8:0]
Data tag RAM array 2[12][32:0][32:0][32:0][8:0]
Data tag RAM array 1[11][32:0][32:0][68:36][8:0]
Data tag RAM array 0[11][32:0][32:0][32:0][8:0]
TLB RAM array 1[10][68:0] -[68:0][7:0]
TLB RAM array 0[9][68:0] -[68:0][7:0]
Global History Buffer arrays 0,1,2,3 normal mode[8][31:0][31:0][31:0][8:0]
Global History Buffer arrays 0,1,2,3 wide mode[8][63:0][63:0][63:0][8:0]
Instruction data RAM array 7 (way 3 high)[7][71:68],[63:32]-[71:68],[63:32][10:0]
Instruction data RAM array 6 (way 3 low)[7][67:64],[31:0]-[67:64],[31:0][10:0]
Instruction data RAM array 5 (way 2 high)[6][71:68],[63:32]-[71:68],[63:32][10:0]
Instruction data RAM array 4 (way 2 low)[6][67:64],[31:0]-[67:64],[31:0][10:0]
Instruction data RAM array 3 (way 1 high)[5][71:68],[63:32]-[71:68],[63:32][10:0]
Instruction data RAM array 2 (way 1 low)[5][67:64],[31:0]-[67:64],[31:0][10:0]
Instruction data RAM array 1 (way 0 high)[4][71:68],[63:32]-[71:68],[63:32][10:0]
Instruction data RAM array 0 (way 0 low)[4][67:64],[31:0]-[67:64],[31:0][10:0]
Instruction tag RAM array 3[3][24:0]-[60:36][8:0]
Instruction tag RAM array 2[3][24:0]-[24:0][8:0]
Instruction tag RAM array 1[2][24:0]-[60:36][8:0]
Instruction tag RAM array 0[2][24:0]-[24:0][8:0]
BTAC RAM target array 1[1][71:36]-[71:36][10:0]
BTAC RAM control array 1[1][31:0]-[31:0][10:0]
BTAC RAM target array 0[0][71:36]-[71:36][10:0]
BTAC RAM control array 0[0][31:0] -[31:0][10:0]

[a] MBISTINDATA[71:0] is sent to all processors

[b] MBISTOUTDATA[287:0] is sent to each processor data output in parallel This column describes the mapping for the data out chunk [71:0]. You must map the chunks to MBISTOUTDATA[287:0] as described in Table 2.6


Table 2.6. MBISTOUTDATA Bit Assignments, with parity
BitsFunction
[287:216]Data Out for CPU3
[215:144]Data Out for CPU2
[143:72]Data Out for CPU1
[71:0]Data Out for CPU0