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2.1.4. Clock and reset

This section describes:


All configurations of the TZASC use a single clock input, aclk. See Clock and reset signals.


The TZASC provides a single reset input, aresetn. See Clock and reset signals.


Clock enable signal that enables the APB slave interface to operate at either:

  • the aclk frequency

  • a divided integer multiple of aclk that is synchronous to aclk.


If you do not use pclken, you must tie it HIGH. This results in the APB slave interface being clocked directly by aclk.