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2.1.1. AXI bus interfaces

The TZASC provides the following AXI bus interfaces:

Each AXI bus interface consists of the following AXI channels:

  • Write Address (AW)

  • Write Data (W)

  • Write Response (B)

  • Read Address (AR)

  • Read Data (R).

See the

AMBA AXI Protocol v1.0 Specification for information about the AXI protocol.

AXI slave interface

Table 2.1 shows the AXI slave interface attributes and their values.

Table 2.1. AXI slave interface attributes
Attribute [a]Value
Read acceptance capabilityEquals the configurable transaction tracker queue depth. If register slices are enabled on AR channel, the read acceptance capability is configurable transaction tracker queue depth plus one.
Write acceptance capabilityEquals the configurable transaction tracker queue depth. If register slices are enabled on AW channel, the write acceptance capability is configurable transaction tracker queue depth plus one.
Combined acceptance capabilityEquals the configurable transaction tracker queue depth. If register slices are enabled on AR and AW channels, the combined acceptance capability is configurable transaction tracker queue depth plus two.
Write interleave depth1
Read data reordering depthEqual to zero. The TZASC does not re-order read data. However the TZASC supports the re-ordering depth of the downstream slave.

[a] SeeGlossary for a description of these AXI attributes.


AXI master interface

Table 2.2 shows the AXI master interface attributes and their values.

Table 2.2. AXI master interface attributes
Attribute [a]Value
Combined issuing capabilityEquals the transaction tracking queue depth that is configurable
Write issuing capabilityEquals the transaction tracking queue depth that is configurable
Read issuing capabilityEquals the transaction tracking queue depth that is configurable

[a] SeeGlossary for a description of these AXI attributes.