This glossary describes some of the terms used in technical documents from ARM.
- Advanced eXtensible Interface (AXI)
A bus protocol that supports separate phases for address or control and data, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels, issuing multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure.
The AXI protocol includes optional extensions for signaling for low-power operation.
- Advanced Microcontroller Bus Architecture (AMBA)
The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides a strategy for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals. AMBA defines a common backbone for SoC modules, and therefore complements a reusable design methodology.
- Advanced Peripheral Bus (APB)
A bus protocol that is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. It connects to the main system bus through a system-to-peripheral bus bridge that helps reduce system power consumption.
A data item stored at an address that is divisible by the number of bytes that defines its data size is said to be aligned. Aligned doublewords, words, and halfwords have addresses that are divisible by eight, four, and two respectively. The terms doubleword-aligned, word-aligned, and halfword-aligned therefore stipulate addresses that are divisible by eight, four, and two respectively. An aligned access is one where the address of the access is aligned to the size of an element of the access.
See Advanced Microcontroller Bus Architecture.
See Advanced Peripheral Bus.
- APB Access Port (APB-AP)
An optional component of the DAP that provides an APB interface to a SoC, usually to its main functional buses.
See APB Access Port.
See Advanced eXtensible Interface.
- AXI channels, channel order and interfaces
The block diagram shows:
the order in which AXI channel signals are described
the master and slave interface conventions for AXI components.
AXI signal names have a one or two letter prefix that denotes the AXI channel as follows:
Write address channel.
Write data channel.
Write response channel.
Read address channel.
Read data channel.
General descriptions of AXI signals use x to represent this prefix, for example, xVALID and xREADY.
- AXI terminology
The following general AXI terms apply to both masters and slaves:
- Active read transaction
A transaction for which the read address transfer has been completed, but the last read data transfer has not been completed.
- Active transfer
A transfer for which the transmitting interface has asserted the xVALID handshake signal, but the receiving interface has not asserted the xREADY handshake signal.
- Active write transaction
A transaction for which the write address or leading write data transfer has been completed, but the write response has not been completed.
- Completed transfer
A transfer for which the handshake using xVALID and xREADY is complete.
The non-handshake signals in a transfer.
An entire burst of transfers, comprising an address transfer, one or more data transfers and, for write transactions only, a response transfer.
- Transmitting interface
An initiator driving the payload and asserting the relevant xVALID signal.
A single exchange of information. That is, a transfer with a single handshake using xVALID and xREADY.
The following AXI terms are master interface attributes. To permit system performance optimization, they must be specified for every component with an AXI master interface:
- Combined issuing capability
The maximum number of active transactions that the interface can generate. It is specified for master interfaces that use combined storage for active write and read transactions. If not specified you can assume it is equal to the sum of the write and read issuing capabilities.
- Read ID capability
The maximum number of different ARID values that the interface can generate for all active read transactions at any one time.
- Read ID width
The number of bits in the ARID bus.
- Read issuing capability
The maximum number of active read transactions that the interface can generate. Must be specified if the combined issuing capability is not specified.
- Write ID capability
The maximum number of different AWID values that the interface can generate for all active write transactions at any one time.
- Write ID width
The number of bits in the AWID and WID buses.
- Write interleave capability
The number of active write transactions for which the interface can transmit data. This is counted from the earliest transaction.
- Write issuing capability
The maximum number of active write transactions that a master interface can generate. Must be specified if the combined issuing capability is not specified.
The following AXI terms are slave interface attributes. To permit performance optimization, they must be specified for every component with an AXI slave interface:
- Combined acceptance capability
The maximum number of active transactions that the interface can accept. It is specified for slave interfaces that use combined storage for active write and read transactions. If not specified then you can assume it is equal to the sum of the write and read acceptance capabilities.
- Read acceptance capability
The maximum number of active read transactions that the interface can accept. Must be specified if the combined acceptance capability is not specified.
- Read data reordering depth
The number of active read transactions for which the interface can transmit data. This is counted from the earliest transaction.
- Write acceptance capability
The maximum number of active write transactions that the interface can accept. Must be specified if the combined acceptance capability is not specified.
- Write interleave depth
The number of active write transactions for which the interface can receive data. This is counted from the earliest transaction.
A group of transfers to consecutive addresses. Because the addresses are consecutive, the device transmitting the data does not have to supply an address for any transfer after the first one. This increases the speed at which the burst occurs. If using an AMBA interface, the transmitting device controls the burst using signals that indicate the length of the burst and how the addresses are incremented.
See Also Beat.
- Digital Signal Processing (DSP)
A variety of algorithms to process signals that have been sampled and converted to digital form. Saturated arithmetic is often used in such algorithms.
See Digital Signal Processing.
The scheme that determines the order of successive bytes of a data word when it is stored in memory.
A mechanism to handle a fault or error event. For example, exceptions handle external interrupts and undefined instructions.
- JTAG Access Port (JTAG-AP)
An optional component of the DAP that provides debugger access to on-chip scan chains.
- Power-on reset
See Cold reset.
Memory operations that have the semantics of a load. See the ARM Architecture Reference Manual for more information.
Registers and instructions that are reserved are Unpredictable unless otherwise stated. Bit positions described as Reserved are UNK/SBZP.
See Should Be Zero.
See Should Be Zero or Preserved.
- Should Be Zero (SBZ)
Software must write as 0, or all 0s for bit fields. Writing any other value produces Unpredictable results.
- Should Be Zero or Preserved (SBZP)
Software must write as 0, or all 0s for a bit field, if the value is being written without having previously been read, or if the register has not been initialized. If the register has previously been read, software must preserve the field value by writing back the value that was read from the same field on the same processor.
An unaligned access is an access where the address of the access is not aligned to the size of an element of the access.
Indicates an instruction that generates an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.
A field that is Unknown on reads and Should Be Zero or Preserved on writes.
An Unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An Unknown value must not be a security hole.
For a processor means the behavior cannot be relied on. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.
For an ARM trace macrocell, means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is Unpredictable. Unpredictable behavior can affect the behavior of the entire system, because the trace macrocell can cause the processor to enter debug state, and external outputs can be used for other purposes.
A 32-bit data item. Words are normally word-aligned in ARM systems.
A data item having a memory address that is divisible by four.
In a word-invariant system, the address of each byte of memory changes when switching between little-endian and big-endian operation, in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of memory always consists of the same four bytes of memory in the same order, regardless of endianness. The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged.
The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions with unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access. ARM strongly recommends that word-invariant systems use the endianness that produces the required byte addresses at all times, apart possibly from very early in their reset handlers before they have set up the endianness, and that this early part of the reset handler uses only aligned word memory accesses.
See Also Byte-invariant.
Operations that have the semantics of a store. See the ARM Architecture Reference Manual for more information.
- Write buffer
A block of high-speed memory implemented to optimize stores to main memory.
- Write completion
The memory system indicates to the processor that a write has been completed at a point in the transaction where the memory system is able to guarantee that the effect of the write is visible to all processors in the system. This is not the case if the write is associated with a memory synchronization primitive, or is to a Device or Strongly Ordered region. In these cases the memory system might only indicate completion of the write when the access has affected the state of the target, unless it is impossible to distinguish between having the effect of the write visible and having the state of target updated.
This stricter requirement for some types of memory ensures that the processor can guarantee that any side-effects of the memory access have taken place. You can use this to prevent the starting of a subsequent operation in the program order until the side-effects are visible.
- Write interleave capability
The number of data-active write transactions for which the interface can transmit data. This is counted from the earliest transaction.
- Write interleave depth
The number of data-active write transactions for which the interface can receive data.