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This preface introduces the ARM® Cortex®-A15 MPCore™ Processor Technical Reference Manual. It contains the following sections:


  • The out-of-order design of the Cortex-A15 MPCore processor pipeline makes it impossible to provide accurate timing information for complex instructions. The timing of an instruction can be affected by factors such as:

    • Other concurrent instructions.

    • Memory system activity.

    • Events outside the instruction flow.

  • Timing information has been provided in the past for some ARM processors to assist in detailed hand tuning of performance critical code sequences or in the development of an instruction scheduler within a compiler. This timing information is not required for producing optimized instruction sequences on the Cortex-A15 MPCore processor. The out-of-order pipeline of the Cortex-A15 MPCore processor can schedule and execute the instructions in an optimal fashion without any instruction reordering required.

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