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7.3. FPU Programmers Model

Table 7.4 shows the FP system registers in the Cortex-M4F FPU.

Table 7.4. Cortex-M4F Floating Point system registers
0xE000EF34FPCCRRW0xC0000000FP Context Control Register
0xE000EF38FPCARRW-FP Context Address Register
0xE000EF3CFPDSCRRW0x00000000FP Default Status Control Register
0xE000EF40MVFR0RO0x10110021Media and VFP Feature Register 0, MVFR0
0xE000EF44MVFR1RO0x11000011Media and VFP Feature Register 1, MVFR1

All Cortex-M4F FPU registers are described in the ARMv7-M Architecture Reference Manual.