The processor implements advanced exception and interrupt handling, as described in the ARMv7-M Architecture Reference Manual.
To reduce interrupt latency, the processor implements both interrupt late-arrival and interrupt tail-chaining mechanisms, as defined by the ARMv7-M architecture:
There is a maximum of a 12 cycle latency from asserting the interrupt to execution of the first instruction of the ISR when the memory being accessed has no wait states being applied. The first instruction to be executed is fetched in parallel to the stack push.
Returns from interrupts similarly take twelve cycles where the instruction being returned to is fetched in parallel to the stack pop.
Tail chaining requires 6 cycles when using zero wait state memory. No stack pushes or pops are performed and only the instruction for the next ISR is fetched.
The processor exception model has the following implementation-defined behavior in addition to the architecturally defined behavior:
exceptions on stacking from HardFault to NMI lockup at NMI priority
exceptions on unstacking from NMI to HardFault lockup at HardFault priority.
To minimize interrupt latency, the processor abandons any
divide instruction to take any pending interrupt. On return from
the interrupt handler, the processor restarts the divide instruction
from the beginning The processor implements the Interruptible-continuable Instruction
field. Load multiple (
LDM) operations and store multiple
STM) operations are interruptible. The ICI field of
the EPSR holds the information required to continue the load or store
multiple from the point where the interrupt occurred.
This means that software must not use load-multiple or store-multiple instructions to access a device or memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in any case where repeated reads or writes might cause inconsistent results or unwanted side-effects.
There are cases when an
the base register:
When the instruction specifies base register write-back, the base register changes to the updated address. An abort restores the original base value.
When the base register is in the register list of an
LDM, and is not the last register in the list, the base register changes to the loaded value.
STM is restarted rather
than continued if:
the instruction faults
the instruction is inside an
LDM has completed a base load, it is continued
from before the base load.