Table 9.1 lists the DWT registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.
|DWT_CYCCNT||RW||Cycle Count Register|
|DWT_CPICNT||RW||CPI Count Register|
|DWT_EXCCNT||RW||Exception Overhead Count Register|
|DWT_SLEEPCNT||RW||Sleep Count Register|
|DWT_LSUCNT||RW||LSU Count Register|
|DWT_FOLDCNT||RW||Folded-instruction Count Register|
|DWT_PCSR||RO||-||Program Counter Sample Register|
|PID4||RO||Peripheral identification registers|
|CID0||RO||Component identification registers|
[a] Possible reset values are:
DWT registers are described in the ARMv7M Architecture Reference Manual. Peripheral Identification. Component Identification registers are described in the ARM CoreSight Components Technical Reference Manual.
Cycle matching functionality is only available in comparator 0.
Data matching functionality is only available in comparator 1.
Data value is only sampled for accesses that do not produce an MPU or bus fault. The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst.
The FUNCTION field in the DWT_FUNCTION1 register is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches.
If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If this bit cannot be set then data matching is unavailable.
PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.