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9.3. DWT Programmers Model

Table 9.1 lists the DWT registers. Depending on the implementation of your processor, some of these registers might not be present. Any register that is configured as not present reads as zero.

Table 9.1. DWT register summary
AddressNameType

Reset

Description
0xE0001000DWT_CTRLRW

See [a]

Control Register
0xE0001004DWT_CYCCNTRW0x00000000Cycle Count Register
0xE0001008DWT_CPICNTRW-CPI Count Register
0xE000100CDWT_EXCCNTRW-Exception Overhead Count Register
0xE0001010DWT_SLEEPCNTRW-Sleep Count Register
0xE0001014DWT_LSUCNTRW-LSU Count Register
0xE0001018DWT_FOLDCNTRW-Folded-instruction Count Register
0xE000101CDWT_PCSRRO-Program Counter Sample Register
0xE0001020DWT_COMP0RW-Comparator Register0
0xE0001024DWT_MASK0RW-Mask Register0
0xE0001028DWT_FUNCTION0RW0x00000000Function Register0
0xE0001030DWT_COMP1RW-Comparator Register1
0xE0001034DWT_MASK1RW-Mask Register1
0xE0001038DWT_FUNCTION1RW0x00000000Function Register1
0xE0001040DWT_COMP2RW-Comparator Register2
0xE0001044DWT_MASK2RW-Mask Register2
0xE0001048DWT_FUNCTION2RW0x00000000Function Register2
0xE0001050DWT_COMP3RW-Comparator Register3
0xE0001054 DWT_MASK3RW-Mask Register3
0xE0001058 DWT_FUNCTION3RW0x00000000Function Register3
0xE0001FD0PID4RO0x04Peripheral identification registers
0xE0001FD4PID5RO0x00
0xE0001FD8PID6RO0x00
0xE0001FDCPID7RO0x00
0xE0001FE0PID0RO0x02
0xE0001FE4PID1RO0xB0
0xE0001FE8PID2RO0x3B
0xE0001FECPID3RO0x00
0xE0001FF0CID0RO0x0DComponent identification registers
0xE0001FF4CID1RO0xE0
0xE0001FF8CID2RO0x05
0xE0001FFCCID3RO0xB1

[a] Possible reset values are:

  • 0x40000000 if four comparators for watchpoints and triggers are present

  • 0x4F000000 if four comparators for watchpoints only are present

  • 0x10000000 if only one comparator is present

  • 0x1F000000 if one comparator for watchpoints and not triggers is present

  • 0x00000000 if DWT is not present.


DWT registers are described in the ARMv7M Architecture Reference Manual. Peripheral Identification. Component Identification registers are described in the ARM CoreSight Components Technical Reference Manual.

Note

  • Cycle matching functionality is only available in comparator 0.

  • Data matching functionality is only available in comparator 1.

  • Data value is only sampled for accesses that do not produce an MPU or bus fault. The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst.

  • The FUNCTION field in the DWT_FUNCTION1 register is overridden for comparators given by DATAVADDR0 and DATAVADDR1 if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches.

  • If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If this bit cannot be set then data matching is unavailable.

  • PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.

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