You copied the Doc URL to your clipboard.

A.1.3. Debug APB interface

Table A.3 shows the debug APB interface signals.

Table A.3. Debug APB interface signals
Signal nameTypeDescription
PCLKENDBGInputAPB clock enable.
PSELDBGInputSelect.
PENABLEDBGInputEnable.
PWRITEDBGInputPeripheral write.
PADDRDBG[11:2]InputAddress. Only word-aligned addresses are supported so bits [1:0] are assumed to be zero.
PADDRDBG31InputIndicates source of APB access. Internal accesses have this signal LOW and external accesses have this signal HIGH..
PWDATADBG[31:0]InputWrite data.
PREADYDBGOutputPeripheral ready.
PSLVERRDBG[a]OutputSlave error.
PRDATADBG[31:0]OutputRead data.

[a] This output is permanently driven LOW in the STM.


Was this page helpful? Yes No