The STM has two asynchronous active LOW resets:
This is used to reset the AXI slave and DMA peripheral request blocks. This is the ARESETn reset domain.
This resets the rest of the STM, including the hardware event observation interface, APB interface register file, and the Trace Generation Unit (TGU). This is the STMRESETn reset domain.
The STM supports both resets being independently asserted, and can be:
trace through AXI reset, ARESETn asserted, STMRESETn not asserted
debug logic being reset without resetting rest of the system, ARESETn not asserted, STMRESETn asserted.