To comply with STPv2, alignment synchronization of the trace stream is done by generating an ASYNC packet followed by a VERSION packet. If timestamping is enabled, a FREQ packet follows the VERSION packet.
The alignment synchronization packets are generated as the first packets after the STM is enabled, and in response to synchronization requests.
In addition, the ASYNCOUT output signal uses a one-cycle pulse to indicate every alignment synchronization carried out by the STM.
The synchronization request sources can be internal or external:
- Internal synchronization requests
An internal synchronization request is made when one of the following occurs:
The STM is enabled.
The STMTSFREQR is programmed.
The STMSYNCR is programmed.
At the end of the synchronization period, defined in terms of number of bytes of trace generated. The synchronization period is defined by the STMSYNCR.
- External synchronization requests
An external synchronization requests comes from outside the STM through the SYNCREQ signal. This enables the system to indicate that the STM must perform alignment synchronization at the next opportunity.
Both internal and external synchronization requests are disabled when the STM is disabled, that is, the STMTCSR.EN bit is set to 0.
Internal and external synchronization requests are combined to avoid excessive ATB bandwidth usage when requests occur near each other.
Insertion of the alignment synchronization sequence usually carries secondary priority to trace generation requests.
This feature is present to address non-typical usage cases. In a typical trace scenario, do not enable this feature, that is, leave the STMAUXCR at its reset value.
The STMAUXCR contains an override control to guarantee synchronization insertion when it is required. You can enable the override by programming the ASYNCPE bit. The behavior of override control is as follows:
If STM cannot insert synchronization request, the request remains pending.
If another synchronization request is received when there is a request pending and override control is set, the priority of synchronization request is escalated.
Trace data is stalled if necessary while a high priority synchronization request is inserted.
The STMAUXCR is implementation defined. Controls defined in this register are not defined in the System Trace Macrocell Programmers’ Model Architecture Specification. There is no guarantee that other implementations of the architecture have the same controls in the STMAUXCR.