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This section describes the following Cortex-R7 MPCore processor
This is the main clock of the Cortex-R7 MPCore processor.
All the processors in the device and the SCU are clocked with a
distributed version of CLK. It
is also the main clock for the ETMs and the local CoreSight infrastructure.
The interrupt controller, global timer, private timers, and
watchdog are clocked with PERIPHCLK. PERIPHCLK must be synchronous with CLK, and the PERIPHCLK clock period,
N, must be configured as a multiple of the CLK clock
period. This multiple N must be equal to, or greater than two.
This is the clock enable signal for the interrupt controller
and timers. The PERIPHCLKEN signal
is generated at CLK clock speed. PERIPHCLKEN HIGH on a CLK rising edge indicates that there
is a corresponding PERIPHCLK rising
Figure 2.2 shows
an example of clocking the peripherals using these enable signals
at a 3:1 ratio.
Figure 2.2. Clocking example on MPCore peripherals
DUALPERIPHCLK and DUALPERIPHCLKEN
This clock and clock enable signal are present if lock-step
or split/lock is implemented. See Clock and control signals for more information on how these signals